Determine the successive bits in a std_logic_vector

[blue_wings_]

Hii all;

i am pretty new vhdl user and i am trying to solve a problem,which is difficult for me nowadays . I have two std_logic_vectors.First one has 5 bits,which must have (11111).Second one has 2040 bits,which is arbitral and i must divide up 2040 bits to 24 outputs that means each output must have 85 bits .First i must determine by using a small vector(5bits) the place of successive 5 bits(11111) in a std_logic_vector,which has 2040 bits.After determing if there are 11111 in a 2040bits vector ,the output should be '1' which is responsible 85 bits where there is 11111 .

to summarize

for example i have 24 outputs each control 85 bits of std_logic-vector(2040bits)
if there is a 11111 in first 85 bits then output1 should be '1'
if there is a 11111 in 86 to 170 bits then output2 should be '1'
if there is a 11111 in 172 to 255 bits then output3 should be '1' so on...

(11111) is the minimum value .it can be bigger to make an output logic '1' Does someone have any idea about it...

Thanks

 

[TrickyDicky]

2040 bits is a massive bus. Where is it coming from? where do these outputs go? you wont have that many pins on a device.

 

[blue_wings_]

I can reduce the number of bits. Actually there is a signal on labview and it has 2040 bits i should send this signal to fpga and then examine it.Like i said i can reduce the number of bits but i havent imagine yet how i can implement it in vhdl...

 

[bking]

Is there any chance you left out a valuable piece of information, like... it's 2040 bits serially presented, or is it truly a 2040 bit wide parallel bus?

 

[blue_wings_]

yes all bits should be examined at the same time.

 

[TrickyDicky]

Are you sure? this seems like a rather odd project.

 

[blue_wings_]

we imagine that there is a selecting device which must be programmed by using vhdl. it must sellect a big product.If the product is big then it must be pushed down from the strap on the device by using airpistol.There are lots of detecting elements and laser ,which should rays the product and then capture it comes from the product on the strap. So we have a tresholdvalue to select whether the product is big or not.if it is then airpistol pushes the product. we have represented a random signal by using labview,which has been represented 2040 bits.This simulates how the device captures the value ,while it works. our treshold value is as is said 11111 the big product must be bigger als 11111 and then we have an 24 air pistols on the strap which control 85 bits if there is no product on the strap then we have (0000000...............000) 2040 bits zero if we elsewehere have some a small product then it seems like (000000000000000000000011000000000000000111000000000000000000101010100000000000..2040) under this situation the airpistol dont push down the product but if it is (00000000000000000000000000......1111110000000000000.....000002040) then the product must be pushed cause it is greater then our tresholdvalue by using airpistol. i wana represent our 24 pistols in vhdl as a output.it can be logic '1' my guestion was that how can i determine a successive 5 bits logic '1' in such a vector and then how can i controll 85 bits and check whether the produkt is big or not big for each pistols??... i hope that i can explain.. Thanks for ur interest...

 

[TrickyDicky]

I really doubt this 2040 bit value comes in as a parrellel bus (no device has that many pins) it will come in serially, or in multiple words. It may then be stored in a register or ram somewhere.

 

[FvM]

Post #7 doesn't seem to talk about real FPGA hardware, rather pure simulation or possibly a combination of simulated data with test hardware. It's not clear if and how the post is related to a real FPGA design.

In simulation there's no pin count restriction, of course. When transferring simulated data, there would be a serial protocol and FPGA internal data storage.

Without detailed information about the implementation conditions: The algorithm can be easily written as behavariol code, so what's the problem at all?

 

[j_andr]

I hope the example below is funny enough to be posted here

---

Code Verilog - [expand]
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module bigguy #( parameter IN_SIZE = 84, BIG_GUY_SIZE = 5 )
(
  input      [IN_SIZE-1:0] size, 
  output                   big_guy
);
     
localparam AND_GATE_NR = IN_SIZE - (BIG_GUY_SIZE - 1);
reg [AND_GATE_NR-1:0] and_gate;
 
integer i;
 
always @(*)
  for (i=0; i<AND_GATE_NR; i=i+1)
     and_gate[i] <= &size[i +: BIG_GUY_SIZE]; // '&' - AND of all five size bits;
 
 
assign big_guy = |and_gate; // '|' - OR of all and_gate bits;
     
endmodule

---

your job is translation to vhdl;

j.a

 

[blue_wings_]

thank you very much all. Think that my job is not simply.. first i should try to implement with small number of bits. j_andr)i must consider your code too..