ASIC_intl
Banned
Supose a square waveform is coming . How will you detect the positive edge and negative edge of the waveform? Provide the circuits to detect the positive and negative edges.
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you can use 2 FF, one triggered by a posedge, the second by a negedgeASIC_intl said:How will you use flip flop to detect a positive edge and also a negative edge?/.../
the solution depends on what you expect as an output;ASIC_intl said:What will u fed tp the D-inputs of the flops?/.../
no, I do not; and I did not;ASIC_intl said:Are u suggesting to fed the waveform/.../
feel some sarcastic - well if you are really interestedDo you work in any...
exectly;ASIC_intl said:/.../So we need to decide about a proper output/.../
it's your task to decide how to code 'negative slope' and 'positive slope';waveform do not distinguish detection/.../
ASIC_intl said:How will you decide about the frequency of the clock to detect the total number of '1' s in any bit pattern coming in your solution for getting no. of '1's?
About the problem of detecting edge I think now u have got the requirment.
Added after 8 minutes:
Hi
In your diagram both detect_1 and detect_2 are not proper outputs to detect both the edges. In case of detect_1 the waveform do not distinguish detection of positive and negative edges. In detect_2 the waveform only detects the positive edge and not the negative edge. So we need to decide about a proper output. It is not told to me/us the nature of the output waveform to detect both the edges. It is only told to find out the way of detection of both positive and negative edges.
Added after 17 minutes:
Hi OLD_NICK
What is the necessity of delaying the waveform. Even without delaying it can detect the positive edge. How will u detect negative edge?
ASIC_intl said:I could not understand how you will distinguish/.../
does it matter ? rtl, fpga implementation, verification;What type of work do u do?
ASIC_intl said:Hi NICK
Please note that it is better if we can think of a circuit that can distinguish between both positive and negative edges.
Even if you fed the waveform in both the inputs of an EXOR gate , you will get a high pulse as soon as it detects a positive edge and it will remain high. IN this wany you will be capable of only detecting the positive edge.
this discussion leads nowhere I'm afraid;ASIC_intl said:/.../
I do not work in HRdo u have openings/.../