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detectiong positive edge and negative edge of a waveform

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ASIC_intl

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Supose a square waveform is coming . How will you detect the positive edge and negative edge of the waveform? Provide the circuits to detect the positive and negative edges.
 

How will you use flip flop to detect a positive edge and also a negative edge? I think u will need circuitry for the porpose of detection of edges.
 

ASIC_intl said:
How will you use flip flop to detect a positive edge and also a negative edge?/.../
you can use 2 FF, one triggered by a posedge, the second by a negedge
and an 'or' gate connected to both FF outputs;
or connect to an XOR gate the clock and clock delayed by several ns;

but I can hardly imagine a usage of such circuit if you test
a square wave -
you need a flag: "at least one pos/neg edge detected" ?
or a short positive pulse triggered by each slope ?
other ?
---
 

What will u fed tp the D-inputs of the flops? What will u fed to the clk inpus of the two flops? Where will u fed the square waveform whose inputs are to be detected?
 

ASIC_intl said:
What will u fed tp the D-inputs of the flops?/.../
the solution depends on what you expect as an output;
draw a picture with the input(s) and required output;
or describe it more detailed;
---
 

I want to detect the positive and negative edges. That's WHAT I want wthatever the output is. Can u give what should be done more clearly by answering the previous question?
 

detect slope - which output is expected ?

43_1218624949.jpg


counting ones - does it explain what I mean ?


---
 

feed the square wave into a delay line (say 500ns delay), then feed the inputs of a 2 i/p exor gate with the original signal and the delayed signal. You'll then get a pulse 500ns long at every edge.

You can also use a comparator and an LPF (simple RC).
 

Hi

Are u suggesting to fed the waveform in the D-input of both the positive and negative edge triggered flops in case of detecting edges to generate the shown waveform form under detect_1. And also to send the outputs of both thflops to a two input or gate.

Do you work in any architecture group? What type of work do you do? What company are u working in?
 

ASIC_intl said:
Are u suggesting to fed the waveform/.../
no, I do not; and I did not;
mainly I tried to get any description of your req.'s from you;
and my answers 'quality' were as good as your specification;
you know the sentence - garbage in - garbage out;
it's not my fault that you assume everybody knows what you have
in mind;
Do you work in any...
feel some sarcastic - well if you are really interested
I work in well known, large company in fpga area
and have some years of experience;
---
 

How will you decide about the frequency of the clock to detect the total number of '1' s in any bit pattern coming in your solution for getting no. of '1's?

About the problem of detecting edge I think now u have got the requirment.

Added after 8 minutes:

Hi

In your diagram both detect_1 and detect_2 are not proper outputs to detect both the edges. In case of detect_1 the waveform do not distinguish detection of positive and negative edges. In detect_2 the waveform only detects the positive edge and not the negative edge. So we need to decide about a proper output. It is not told to me/us the nature of the output waveform to detect both the edges. It is only told to find out the way of detection of both positive and negative edges.

Added after 17 minutes:

Hi OLD_NICK

What is the necessity of delaying the waveform. Even without delaying it can detect the positive edge. How will u detect negative edge?
 

ASIC_intl said:
/.../So we need to decide about a proper output/.../
exectly;
this is a question I asked couple of times - what output you need;
waveform do not distinguish detection/.../
it's your task to decide how to code 'negative slope' and 'positive slope';
you can add one more bit as an output so you will have information
of the slope and the direction, you can code it as pulse length [more difficult],
you can code it as an output pulse shift;
in the option 2&3 you need a system clock that is at least 6x faster then
your tested waveform;
---
 

j_andr

I could not understand how you will distinguish between pos and neg edge. What do u mean by 2&3.?

What type of work do u do? Do you also decide architecture of circuits before writing RTLs and after specification?
 

ASIC_intl said:
How will you decide about the frequency of the clock to detect the total number of '1' s in any bit pattern coming in your solution for getting no. of '1's?

About the problem of detecting edge I think now u have got the requirment.

Added after 8 minutes:

Hi

In your diagram both detect_1 and detect_2 are not proper outputs to detect both the edges. In case of detect_1 the waveform do not distinguish detection of positive and negative edges. In detect_2 the waveform only detects the positive edge and not the negative edge. So we need to decide about a proper output. It is not told to me/us the nature of the output waveform to detect both the edges. It is only told to find out the way of detection of both positive and negative edges.

Added after 17 minutes:

Hi OLD_NICK

What is the necessity of delaying the waveform. Even without delaying it can detect the positive edge. How will u detect negative edge?

I'm not sure what you mean?

I have this very edge detection circuit working in a camera control system I've built, and it works a treat. The wave form is delayed, in order to allow the exor to detect edges (falling and rising). The period of delay gives the length of the pulse produced at each edge (adjust depending on the frequency of the square wave) - (it gives no indication on whether it was a falling or rising edge, just that there was an edge).
I'm not sure what you mean when you say 'it can detect a positive edge' without delaying. An exor gate cannot do that.
I'm not sure what exactly you're after, but if it is just to have a pulse indicating an edge, then an EXOR and delay line is as goosd a solution as I know.
 

Hi NICK

Please note that it is better if we can think of a circuit that can distinguish between both positive and negative edges.

Even if you fed the waveform in both the inputs of an EXOR gate , you will get a high pulse as soon as it detects a positive edge and it will remain high. IN this wany you will be capable of only detecting the positive edge.
 

ASIC_intl said:
I could not understand how you will distinguish/.../

42_1218634675.jpg


btw. - if it's really a square wave - why you need to detect anything ?
you already have all information - the pos and neg edges;
your task makes sense if the 'square wave' is not square;

What type of work do u do?
does it matter ? rtl, fpga implementation, verification;
---
 

ASIC_intl said:
Hi NICK

Please note that it is better if we can think of a circuit that can distinguish between both positive and negative edges.

Even if you fed the waveform in both the inputs of an EXOR gate , you will get a high pulse as soon as it detects a positive edge and it will remain high. IN this wany you will be capable of only detecting the positive edge.

I have been and am still using this circuit, and I can assure you that it works.

What you've said is quite wrong, draw the waveforms out (make sure you understand what an EXOR does) and you'll see.

Specify the problem properly, and you may get the answers you're looking for.
You can use the pulses in conjunction with the original clock signal to resolve whether it was a rising or falling edge that was detected at each pulse.
 

Hi j_andr

The detection will be more appropriate if you do not know about the input signal and you want to detect presence of positive and negative edges.
You are right here.

What I wrote above is more general. To make the problem simple weare first thinking of square wave as the input. And I want to detect its edges.

If you search in google about detection of edges you will find some patents on it.

In your ansawer as I understand you will distinguish the pos and neg edges by seeing their phase. What will be the phase value for pos edge and neg edge?

Added after 7 minutes:

Hi j_andr

I do architecture and placement and routing. Do u do architecture development?

do u have openings in your company for junior level engineers now?Hi
 

ASIC_intl said:
this discussion leads nowhere I'm afraid;
my last notes:
you have to have a clear view how the 'detected slope' signal/signals will be used;
this mainly determines the detection method;
I assume you need to trigger an action on a positive slope and a different
action on a negative one - so define logic sensitive on pos. edge and another
logic reacting on neg. edge and synchronize both later on to your system clock;

do u have openings/.../
I do not work in HR
---
 

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