detectiong positive edge and negative edge of a waveform

[ASIC_intl]

Your assumption is o.k.
The input should be a square wave signal for the time being. It will be better if we later on can think of the circuit that can detect pos and neg edges of any type of SIGNALS coming.

I hope it is clear.




I know u are not hr. but u must be knowing about vacancies in your group.

Added after 3 hours 56 minutes:

hi j_andr

Any solution?

Added after 4 minutes:

Hi NICK

Can u please draw the waveform of what you are saying by delaying it by 500 ns with a EXOR gate?

 

[kulkarni_saurabh]

Hi ASIC_intl,

Posedge and negedge detection is a common requirement in microprocessors. One application could be to detect edge/level triggered events on certain GPIO inputs. I was in a team which was responsible for designing the GPIO module of a processor and we had to implement an event detection functionality based on the following register fields (to be configured through assembly):

BIT_NAME~~~~~VALUE~~~~~FUNCTIONALITY
LEVEL~~~~~~~~ 1 ~~~~~Detect level sensitive event
~~~~~~~~~~~~~0 ~~~~~Detect edge sensitive event

POLARITY~~~~~ 1 ~~~~~Detect posedge/high level signal
~~~~~~~~~~~~~0 ~~~~~Detect negedge/low level signal

In order to implement the edge sensitive functionality we used the following circuit. This circuit has two advantages:

1. It consists of purely digital components (unlike the filters as suggested in an earlier reply).
2. Secondly, this circuit uses only +ve edge triggered FFs. (Dual edge triggering is generally not recommended in ASICs).

The verilog pseudo code for the circuit is:

DFF FF1 (.clk(clk), .rst(rst), .d(In), .q(Q1) );
DFF FF2 (.clk(clk), .rst(rst), .d(Q1), .q(Q2) );

assign Q_posedge = Q1 & ~Q2;
assign Q_negedge = ~Q1 & Q2;

where "In" is the input signal whose edges you need to detect.
Q_posedge and Q_negedge are signals which are asserted whenever a posedge or negedge occurs on the input.
Mind you, the width of Q_posedge and Q_negedge is 1 clk cycle. You may want to latch it if you want an output signal of higher width. In our case, a width of 1 clk cycle was enough.

Using the above pseudo code you can draw the schematic and work out the waveforms.

In case you are not able to do so, let me know and I'll post the waveforms too.

Regards,
Saurabh

 

[karikalan_t79]

edge detector

signal and not signal - rising
not signal and singal = falling
signal xor singnal = both