desinging folded cascode opamp

[ginny47889]

hi
i m trying to design a folded cascode opamp(90nm process technology)..but it is showing very gain..around 40db..with vdd=1.2V...can anybody suggest me the ways to increase the gain of this opamp..

thnks..

 

[dgnani]

increase output resistance, by increasing L of current sources and gm of cascodes
increase gm by increasing diff pair W/L and/or I, if all else fails operate the diff pair in weak inversion

 

[ginny47889]

sir
pls take a look at my simulation settings..m nt sure if i have modeled it correctly..
*** Simulation Settings - Parameters and SPICE Options *********

MMOSFET_N_5 N15 N15 N11 Gnd NMOS L=450n W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_6 OUT N15 N13 Gnd NMOS L=450n W=22u AD=66p PD=24u AS=66p PS=24u
vSource_v_dc_1 N62 Gnd 0.25
vbias N56 Gnd 0.5
MMOSFET_P_1 N3 N56 N15 Vdd PMOS L=450n W=28u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_2 N4 N56 OUT Vdd PMOS L=450n W=28u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_1 N3 N_1 Other Gnd NMOS L=450n W=30u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_2 N4 N_2 Other Gnd NMOS L=450n W=30u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 N13 N11 Gnd Gnd NMOS L=450n W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_4 N11 N11 Gnd Gnd NMOS L=450n W=22u AD=66p PD=24u AS=66p PS=24u
vdd Vdd Gnd 1.2
CCapacitor_1 OUT Gnd 200f
vSource_v_dc_2 N59 Gnd 0.7
MMOSFET_P_3 Vdd N59 N3 Vdd PMOS L=450n W=1.2u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_4 Vdd N59 N4 Vdd PMOS L=450n W=1.2u AD=66p PD=24u AS=66p PS=24u
MN7 Other N62 Gnd Gnd NMOS L=450n W=45u AD=66p PD=24u AS=66p PS=24u
vSource_v_dc_3 N63 Gnd 0.32
vSource_v_ac_1 N_1 N63 0.0 AC 0.025 0.0
vSource_v_ac_2 N_2 N63 0.0 AC 0.025 -180

********* Simulation Settings - Analysis section *********
.op
.ac dec 10 1 100mega analysisname=NOISE

********* Simulation Settings - Additional SPICE commands *********
.measure ac gain max VDB(OUT)
.print vdb(OUT)



.end

 

[dgnani]

the AC gain is
v(OUT)/(v(N_1)-v(N_2))

vdb(OUT) will be equivalent only if
v(N_1)-v(N_2)=1

while in your case you chose small AC sources !?

Set each AC source to an amplitude of 0.5, remember this is a small signal analysis... a large AC signal does not change the operating point

 

[thanapandi]

Hi,
How much current you are using that opamp, Increse your current or increase your mos length...

 

[dgnani]

Hi,
How much current you are using that opamp, Increse your current or increase your mos length...

Just in case it was not clear from the previous post, he already has quite a bit of gain (66dB), he just did not measure it correctly

 

[katayoun]

hi.
i m trying to design a folded cascode opamp(90nm process technology)
i want to achieve
GBW: 1/7089E+09MHz
phase margine: -1/0422E+02 degree
gain DC: 4/0045E+01 dB
with supply power:1.8V
i need size of W and L....simulation setting.
please help me az soon as possible.plz.
thx

 

[katayoun]

hi.plz send me size of all w and L

 

[shrikant_joshi7]

increase the length of load transistors to increase their output resistances .
Av=gm1((ro1.gm3.ro3)||(gm5.ro5.ro7))
Do not incerase the length of M1-M4 much as it will increase the capacitance.
Try this:
M1,M2=240,400n
M3,M4=600,400n
M5M6M7M8=960,800n
M9=240,400n
M10=3.6u,400n
Iref=20u

---------- Post added at 02:05 ---------- Previous post was at 02:04 ----------

increase the length of load transistors to increase their output resistances .
Av=gm1((ro1.gm3.ro3)||(gm5.ro5.ro7))
Do not incerase the length of M1-M4 much as it will increase the capacitance.
Try this:
M1,M2=240,400n
M3,M4=600,400n
M5M6M7M8=960,800n
M9=240,400n
M10=3.6u,400n
Iref=20u