sridhara
Member level 4
100 mhz pll
my problem statement is to generate clock of 100 MHz using pll and the jitter must be minimum.... my tuning range of vco can be of our own choice .........problem .......i am not able to fix the other design constraints like
* phase margin
*charge pump gain
*charge pump current
help me in choosing (or finding)these values for very less jitter clock //...
or tell me some good links where can we get the design procedure....
how can we fix the gain of vco and phase detector....is it right that kvco and kpd cant be fixed and can be obtained only after design.....????
also tell me in what way does the phase margin determine the performance of pll
.....
my problem statement is to generate clock of 100 MHz using pll and the jitter must be minimum.... my tuning range of vco can be of our own choice .........problem .......i am not able to fix the other design constraints like
* phase margin
*charge pump gain
*charge pump current
help me in choosing (or finding)these values for very less jitter clock //...
or tell me some good links where can we get the design procedure....
how can we fix the gain of vco and phase detector....is it right that kvco and kpd cant be fixed and can be obtained only after design.....????
also tell me in what way does the phase margin determine the performance of pll
.....