my problem statement is to generate clock of 100 MHz using pll and the jitter must be minimum.... my tuning range of vco can be of our own choice .........problem .......i am not able to fix the other design constraints like
* phase margin
*charge pump gain
*charge pump current
help me in choosing (or finding)these values for very less jitter clock //...
or tell me some good links where can we get the design procedure....
how can we fix the gain of vco and phase detector....is it right that kvco and kpd cant be fixed and can be obtained only after design.....????
also tell me in what way does the phase margin determine the performance of pll
.....
all of these must be done , using a system analysis of the PLL , u need to make the model , simulate and sweep all these paramters and choose the best which get ur spc's
there are alot of discussion here about PLL and also a lot of books
can u please explain me how u arrived at this(i want the formulas and theory behind this..) ....i am exactly in need of this datas and if possible quote any links for the same.....
thanks in advance.....
my problem statement is to generate clock of 100 MHz using pll and the jitter must be minimum.... my tuning range of vco can be of our own choice .........problem .......i am not able to fix the other design constraints like
* phase margin
*charge pump gain
*charge pump current
help me in choosing (or finding)these values for very less jitter clock //...
or tell me some good links where can we get the design procedure....
how can we fix the gain of vco and phase detector....is it right that kvco and kpd cant be fixed and can be obtained only after design.....????
also tell me in what way does the phase margin determine the performance of pll
.....
Hi all,
Dear hung_wai_ming@hotmail.com can you through more light on how to compute in general this parameter from where you starts and what parameters/factor to take in considerations.
Thanks in advance.