design transistor size in cmos process

[saber67]

hi
please help me to design calculation of transistor size in cmos process

thanks

 

[DharmaSlice]

Hi saber67,

That’s a very open ended question. But I’d say as a starting point you can decide what current you want passing through the transistor and what overdive voltage is required (Vgs – Vt) --- where Vgs is the gate-source voltage and Vt is the threshold voltage.

Use the equation

IDS = K’(W/L)*(Vgs – Vt)^2

Where K’ is process parameters.

I suppose Im showing the formula here in the hope you will find this online for a better explanation 

https://books.google.ie/books?id=97...=onepage&q=IDS = K’(W/L)*(Vgs – Vt)^2&f=false

 

[dick_freebird]

Start with the desired outcome(s) and work backward in
simulation or calculation. You don't have a desired outcome.
So any direction is as good as another.