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Design to state position of first one from lsb every clock for parallel data coming

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fragnen

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Can you please provide a design whose output will state the location of the first '1' from the LSB for an incoming parallel bit stream every clock?
 

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No it is not. Please reply.

You seem to have a misconception of what this forum is about. Members will help you with answering questions you may have on a variety of electronics related topics. They will assist you in resolving problems you may have in code or concepts. What members are unlikely to help with is: Doing your work for you.

You have an assignment or a need to have this circuit then do one or more of the following:
a) design it yourself
b) hire someone to design it, if you are not capable of designing such a circuit
c) try to design it and ask questions on the forum (showing what you have done) about any problems with your circuit that you can't figure out how to fix.
d) search the internet for your answer

Of the various options you will learn the most by doing either a or c.
 

std_match

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Can you please provide a design whose output will state the location of the first '1' from the LSB for an incoming parallel bit stream every clock?

What you want is identical to a "priority encoder."
 

vGoodtimes

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There are 2-3 ways to code this. The obvious is a for loop from msb to lsb. This actually works when the synthesis tool understands and implements this in a good way. The fancy way uses "bitscan" with (x) & (-x). This expression returns a one-hot vector with the lowest 1 being the only bit set. The third method is manually generating the logic for a priority encoder.

There is also a priority encoder implementation that takes a 1-hot vector and does the and-or map-reduce with 10101010, 11001100, 11110000, etc...
 

fragnen

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There are 2-3 ways to code this. The obvious is a for loop from msb to lsb. This actually works when the synthesis tool understands and implements this in a good way. The fancy way uses "bitscan" with (x) & (-x). This expression returns a one-hot vector with the lowest 1 being the only bit set. The third method is manually generating the logic for a priority encoder.

There is also a priority encoder implementation that takes a 1-hot vector and does the and-or map-reduce with 10101010, 11001100, 11110000, etc...

Will the rtl with for loop be synthesizable ? But for loop reduces the work. If it is a priority encoder it is a big code when the width of the input data is parametrized.

What is the bitscan mathod. What is x and what is -x?

Thank you.
 

FvM

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What is x and what is -x?
Review this previous thread for an explanation. https://www.edaboard.com/showthread...cate-the-addresses-of-1-s-in-std_logic_vector

In my view, a behavioral description of the intended logic, typically using a for loop is a straightforward approach to synthesize it, as long as you don't have additional requirements, e.g. implementing pipelining or enforcing a specific hardware implementation like using carry chains to speed up the design.

Some synthesis tools have difficulties to implement non-arithmetic problems like priority encoder optimally following a behavioral description, but they are always able to implement it correctly.
 

stanford

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Code:
for (i=0; i<WIDTH, i=i+1) begin
  if (input[i]) begin
    position = i;
    break;
  end
end
 
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fragnen

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Code:
for (i=0; i<WIDTH, i=i+1) begin
  if (input[i]) begin
    position = i;
    break;
  end
end

Will not in non synthesizable due to this break inside the for loop as this break is stopping the loop to continue?

Some synthesis tools have difficulties to implement non-arithmetic problems like priority encoder optimally following a behavioral description, but they are always able to implement it correctly.

You stated that some synthesis tools have difficulty to implement non-arithmetic problems. You also wrote that they, the synthesis tools, are always to implement non-arithmetic problems correctly? How both can be valid? Did you intend to state something else by your above quoted statement then?
 

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Will not in non synthesizable due to this break inside the for loop as this break is stopping the loop to continue?



You stated that some synthesis tools have difficulty to implement non-arithmetic problems. You also wrote that they, the synthesis tools, are always to implement non-arithmetic problems correctly? How both can be valid? Did you intend to state something else by your above quoted statement then?

It's clear that you are not fluent in English, hopefully breaking FvM's statement into individual concepts will help:

1) synthesis tools have difficulties implementing non-arithmetic problems like priority encoders.
2) difficult synthesis usually means you end up with non-optimal synthesis results.
3) synthesis tools (unless they have a bug) should produce a result that is functionally correct, but may not be the optimal result (see 2).
 
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Akanimo

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Hi,

You can also code a priority encoder without using the for-loop.

Whichever method you use, one thing you have to realize is that you have to feed the data into the priority encoder like so:
20190508_001018.jpg

A code for a priority encoder can also be written with an IF/ELSIF/ELSE STATEMENT in a process that is not sensitive to clock but is sensitive to all other required inputs.

First of all make a priority encoder with the method of your choosing and then make the connections as in the attachment provided. Without interchanging the bit positions like in the attachments, the implementation will not be successful.
 
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    fragnen

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