Design TDO connection for JTAG controller

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haianh

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Hi everyone,

I have question about TDO signal. My design have some TDO signal from ID code, IR, Bypass and BIST. All of them are clocked to failing edge of TCK.

Then I have a MUX of all TDO into TDut. Do I need one more flipflop to clock the TDut to the failing edge of TCK before it goes to three-state output buffer to become output pad TDO?

If I did that, my TDO is delayed one more cycle and maybe it was wrong.

It is not clear in the 1149.1 standard and make me confuse. Thanks any help for my problem
 

You do not need an additional flipflop, as you noted it would add one extra delay state and it would not work correctly.

A cleaner approach would be to have all internal logic operate on rising edge only and throw in the neg edge delay after the tdo mux. You are now using three neg edge delays when you really only need one.

That neg edge flop is only needed on the tdo signal that leaves the chip and is daisy chained with other chips jtag logic. Without it you could have a hold time issue. If you daisy chain with other taps inside your chip then your synthesys tool will take care of hold time for you .

John Eaton
 
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    haianh

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Thanks John :thumbsup:

I understood the cleaner approach you said, it is better way but I can not do it. My design have some daisy chain in BIST logic then it has its own TDO signal that is clocked to failing edge of TCK. It is fixed and I can not remove those flipflops before the MUX of TDO.

I just wonder if I do not have one flipflop after the MUX and before the output buffer, it follow the standard or not? And does it affect to output TDO (fanout/delay/anything)?
 

I just wonder if I do not have one flipflop after the MUX and before the output buffer, it follow the standard or not? And does it affect to output TDO (fanout/delay/anything)?


If any of your chains sync to the neg edge then you must sync all of them before muxing them out to the TDO pad. If all of your chains are pos edged synced then you can add a neg edge flop
between the mux and the tdo pad.

If your tdo is going to an internal daisy chain then you can simply pass on the pos edge synced signals. Synthesys will handle the hold time issues

You can send a neg edged synced TDO to an internal daisy chain but it cuts your max clock rate in half.


John Eaton
 


Yes, the daisy chain is already clocked to neg edge TCK inside the BIST logic and connect to BIST_TDO. Then I sync all other TDO (ID code, IR, Bypass) to neg edge TCK before mux all of them to TDut. TDut will be going out to TDO pad and do not connect to any internal daisy chain.

So the correct answer is I do not need the flipflop after the MUX, just add the output buffer after TDut and connect it to TDO pad.

Thank you very much John
 

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