haianh
Newbie level 6

Hi everyone,
I have question about TDO signal. My design have some TDO signal from ID code, IR, Bypass and BIST. All of them are clocked to failing edge of TCK.
Then I have a MUX of all TDO into TD
ut. Do I need one more flipflop to clock the TD
ut to the failing edge of TCK before it goes to three-state output buffer to become output pad TDO?
If I did that, my TDO is delayed one more cycle and maybe it was wrong.
It is not clear in the 1149.1 standard and make me confuse. Thanks any help for my problem
I have question about TDO signal. My design have some TDO signal from ID code, IR, Bypass and BIST. All of them are clocked to failing edge of TCK.
Then I have a MUX of all TDO into TD
If I did that, my TDO is delayed one more cycle and maybe it was wrong.
It is not clear in the 1149.1 standard and make me confuse. Thanks any help for my problem