Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Usually the I/O PAD provided by foundary is too big.
Some company will design their own I/O PAD for area consideration.
There are many books and IEEE papers talking about this topic. You may find them via google.
The whole chip ESD design/consideration is more than just I/O PAD itself. Most foundary will provide some guidelines and suggestion about the whole chip ESD design consideration. You may find them in the Layout rule documents.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.