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Usually the I/O PAD provided by foundary is too big.
Some company will design their own I/O PAD for area consideration.
There are many books and IEEE papers talking about this topic. You may find them via google.
The whole chip ESD design/consideration is more than just I/O PAD itself. Most foundary will provide some guidelines and suggestion about the whole chip ESD design consideration. You may find them in the Layout rule documents.
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