Design for implementing a delay-line

[yifen]

When we want to implement a delay-line(2048 taps, 16bits for each taps), which one of the following design is better (small chip area / lower power consumption)?

1. Use shift register.
2. Use two port SRAM(1R/1W).

 

[sameer_dlh25]

Re: About delay-line

Hi yifen,

I am not clear with the of the options you mentioned here.

SRAM as a delay lines means you need to have address decoder. For the size mentioned here it will have considerable area for decoding. And if you want to perform read and write simultaneously then you need duel address decoding.

I think best option is use a FIFO in place of SRAM or shift register to save power and area on the size mentioned here.
I hope this will help:|

 

[prajit]

About delay-line

Shift register/FIFO is the best option ..u will have some some intial latency ..but it will not be of much problem compared SRAM as mentioned by Mr.Sameer

 

[tdminion]

About delay-line

Not clear on the SRAM implemenation, but in general, when you are talking multiple 1000's of registers vs SRAM, SRAM is lower power and smaller. There is overhead associated with the SRAM, but the storage elements are smaller and lower power. As the number of bits required increases the SRAM becomes more efficient