design flow fpga prototype asic design

Status
Not open for further replies.
M

manfer

Newbie level 6
Joined
Jan 22, 2008
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,352
Hy I'm looking for a design flow for fpga prototype to asic design. I want to know what are the constraints that exist and what is the diference between block ip for fpga and for asic
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…