Design Compiler Segmentation Fault

[a_mythpi]

Hello..

I am trying to obtain a gate level netlist for my rtl code. I have two versions of the same design. One is a larger version of the same design. I am able to obtain the gate level netlist for the smaller design ( runs for around 8-9 hrs) but when I do the same for the other one it gives segmentation fault after optimising delay and timing for around 12 hrs. I am using design vision 2012-SP5.
Can anyone suggest me how I can solve this problem.

Thanks

 

[eklikeroomys]

Maybe your machine runs out of memory with the larger design?

 

[mail4idle2]

Check memory capabilities when you have submitted the task.

 

[a_mythpi]

Hello...

I am running it on the server which has sufficient memory . I believe memory shold not be a problem in this case.

 

[maulin sheth]

Hello,

Segmentation Fault mostly comes when there is a problem with memory.
When we are accessing the memory in wrong manner, thn also there are chances of segmentation fault.
Also check where your log is created..may be there is insufficient memory...

 

[rca]

Could you indicate the gate count, to check that run time is normal?
Are you able to try with an other version?
Did you have too aggressive constraints?

 

[kirteshmiet]

it may be the case that your segments are quite high so memory is becoming less for the design that is why it is not producing the output. or may be you are optimizing more and more so when it will try to optimise more then memory could be the problem.. so check with your scripts please hope your problem will be solve.