jaydip said:
what commands are you executing on dc_shell prompt? in your constraints file you would find false_path which could be preventing dc ..
Happy New Year everybody
Following is my simple script. I indeed added max_delay constraints to the outputs and registers which I think is why DC reports false_path warning. But I don't add those max_delay constraints to the outputs and registers, DC treats those paths as unconstrained paths which is another part I feel confused. Thank you for spending timing looking into it.
# Define system clock period
set clk_period 1
set clk_name clk
create_clock -period $clk_period clk
set_drive 0 clk
set_clock_uncertainty -setup [expr 0.1*$clk_period] $clk_name
set_operating_conditions TYPICAL
set auto_wire_load_selection true
# Define design environment
set ALL_INS_EX_CLK [remove_from_collection [all_inputs] [get_ports clk]]
set max_cap [expr [load_of saed90nm_typ/AND2X1/IN1]*5 ]
set_driving_cell -lib_cell DFFX1 -pin Q $ALL_INS_EX_CLK
set_drive 0 {clk rstN}
set_load $max_cap [all_outputs]
# Define design constraints
set_max_area 0
#set_input_delay $clk_q_plus_inv -clock $clk_name [all_inputs]
set_input_delay 0.08 -clock $clk_name [all_inputs]
set_output_delay 0.05 -clock $clk_name [all_outputs]
set max_delay $clk_period
set_max_delay $max_delay -to [all_outputs]
set_max_delay $max_delay -to [all_registers -data_pins]
compile -map_effort medium
create_clock clk -period 0.5
optimize_registers -sync_trans multiclass
Added after 5 minutes:
yx.yang said:
I don't know why you will get this warning.
But if your want to check whether your retiming work or not, there are two methord:
1): set clock, to see the clock frequency different for retiminged design and not retiminged synthesis result.
2): use simulation to see the a0_reg[?] / a1_reg[?] ../b0_reg[?] / b1_reg[?] ... value in gate level simulation.
By the way: if you use retiming, you may get some problem in LEC check. So you would better partition the piple by hand, not through synthesis tool.
I checked the design, because of the "false_path" constraints warnings, no retiming happened. But I indeed tried to use DC pipeline command to explicitly tell DC to partition the design into 3 stages, this works very well. But I just want to figure out why I cannot use optimize_registers and insert Regs at the inputs. The script is list above.