Dear all,
In my design, I want to implement a single port, 11x32bit register file. I have chosen the DW IP from DCW_ram_r_w_s_dff, which is a Synchronous Write-Port, Asynchronous Read-Port RAM (Flip-Flop-Based). After synthesis, the gate count is about 6600xNAND2. It seems a little larger for me.So I am wondering whether memory compiler can generate a smaller regfile?
Hi,
1.I think registers maybe more suitable.
2. If you prefer memory. You should use rapid compiler to generate memory. Since rapid compiler use vender library to generate memory, while synopsys DW is not mapped to vendor library.
yes, memory compiler can generate a small one, we use artison's memory
compiler.
eexuke said:
Dear all,
In my design, I want to implement a single port, 11x32bit register file. I have chosen the DW IP from DCW_ram_r_w_s_dff, which is a Synchronous Write-Port, Asynchronous Read-Port RAM (Flip-Flop-Based). After synthesis, the gate count is about 6600xNAND2. It seems a little larger for me.So I am wondering whether memory compiler can generate a smaller regfile?