I dont know if Synopsys DC has in-built TEST compiler or not, but yes if you want to do full-scan_boundasy scan you can use the tool DFT Compiler from Synopsys. Your first step should be to read in the systhesized netlist which you got rom DC as input to the DFT Compiler tool.
Few essential commands are
read_vhdl -netlist ./GCD_Cal.vhd
set_dft_signal -view existing_dft -type ScanClock -port clk -timing [list 45 55]
set_dft_signal -view existing_dft -type Reset -port rst -active_state 1
create_port -direction in SCAN_ENABLE
create_port -direction in SCAN_IN
create_port -direction out SCAN_OUT
set_dft_signal -view existing_dft -type ScanDataIn -port SCAN_IN
set_dft_signal -view existing_dft -type ScanDataOut -port SCAN_OUT
set_dft_signal -view existing_dft -type ScanEnable -port SCAN_ENABLE -active_state 1
set_dft_signal -view existing_dft -type ScanClock -port clk -timing [list 45 55]
set_dft_signal -view existing_dft -type Reset -port rst -active_state 1
# Insert the Scan Chain
insert_dft
write_file -format verilog -hierarchy -output ./GCD_Scan.v
write_file -format ddc -hierarchy -output ./GCD_Scan.ddc
write_test_protocol -output ./GCD_Scan.spf