Design big delay element

[tomph]

Hello,
In my circuit I needs 3us delay element . It is too big if using Resistor and Capacitors would you please help me to suggest any possible ways to design that long (3us) delay. Thank you very much.
Tom

 

[hyy95120]

signal ->ADC->digital FIFO delay->DAC

You'll need big FIFO RAM depending on your signal's bandwidth.

if u use R and C, the High Freq will be cut off.

 

[mark_nctu]

You can use curent to generate a small current source and chagre a mos to make the large delay time.

 

[tomph]

to hyy95120: thanks for your comments

signal ->ADC->digital FIFO delay->DAC

You'll need big FIFO RAM depending on your signal's bandwidth.

if u use R and C, the High Freq will be cut off.

Actually, I 'm not good at FIFO.

To amrk_nctu:

You can use curent to generate a small current source and chagre a mos to make the large delay time.

Could you please be more specific. I 'm interested in your method.
Thanks,
Tom

 

[butterfish]

You can use curent to generate a small current source and chagre a mos to make the large delay time.

Agree, current source+capacitor is a simple way.

 

[hyy95120]

doesn't current source+cap act the same like RC? the bandwidth is severely limited, high frequency will be cut off.

let's say, u want to delay with small current, which translate to longer charge time for the cap, which translate to poor high frequency response.

if you have signal bandwidth much larger than the 3us(330KHz) delay, the only Analog way I can think of doing this is using a "Sample and Hold" Pipeline with switch capacitor technology. for each clock cycle, you "Sample" an input signal and "Pass" it to the next stage, exactly the same way as Digital FIFO, except that you don't need to do the A/D converting.

 

[butterfish]

doesn't current source+cap act the same like RC? the bandwidth is severely limited, high frequency will be cut off.

let's say, u want to delay with small current, which translate to longer charge time for the cap, which translate to poor high frequency response.

if you have signal bandwidth much larger than the 3us(330KHz) delay, the only Analog way I can think of doing this is using a "Sample and Hold" Pipeline with switch capacitor technology. for each clock cycle, you "Sample" an input signal and "Pass" it to the next stage, exactly the same way as Digital FIFO, except that you don't need to do the A/D converting.

You are right. RC,IC are only for delay edge.
If delay a small signal, it will be complex.

 

[rf_ray]

If you are dealing with digital signal, then use counter (could be complicated). If it's small signal I don't think there is anyway you can achieve that (The delay is simply too big)

 

[vomit]

Have you checked the products of the company https://www.datadelay.com/ ?

 

[mydreamhouse]

i have the same requirement
i want to make a power up circuit , no exteral resistor and capacitor is allowed ,but ,it need a delay that is large than 120us
i think switch capacitor and mirror current and meet the implement

 

[tanuki]

Please describe the function you need more completely.

As you can see from the suggestions there are many kinds of "delays".

I'll guess.

Low precision solution: Since you mentioned a RC element. I think you want a edge triggered delay. Use a one-shot timer (aka Monostable Multivibrator, i.g. MM74HC4538). 3us delay is easily handled by this device.

Higher precision solution:
If you need a precise edge triggered delay, use a crystal oscillator (you may already have one in the design), use a loadable down counter to count down the 3 us time.

Like many things, the answer can be no better than the question. Tell us what you're wanting to do.

 

[analog123]

Mirror cap may be right

 

[butterfish]

If you are dealing with digital signal, then use counter (could be complicated). If it's small signal I don't think there is anyway you can achieve that (The delay is simply too big)

by theroy: I think AD+digital delay (Z^-1)+DA can achieve small signal delay.