Current-starved Inverter as delay element.

[melkord]

Hello,
My supervisor suggested me not to use the delay circuit shown below.
The reason is we cannot guarantee if ID of PMOS and NMOS to be the same.
While I completely agree with this statement, I still do not understand the relevant of it to the functionality of the circuit.
Even if the current is imbalanced, the circuit still delays the input signal.

Can someone help me to understand the context here in case I missed something?
If it is true that this circuit is just for concept or educational purpose, is there any alternative that can delay both rising and falling edge?

 

[dick_freebird]

"Pedantically true, and so what?"

The consistency of delay will be better than a plain inverter chain. N drive and P drive are never identical if you look close enough. To the argument, I'd demand a delay min/max requirement to be met. Without that it's pointless pursuit of perfection.

Did you sign up for absolute perfection across PVT?

 

[ljp2706]

Hello,
My supervisor suggested me not to use the delay circuit shown below.
The reason is we cannot guarantee if ID of PMOS and NMOS to be the same.
While I completely agree with this statement, I still do not understand the relevant of it to the functionality of the circuit.
Even if the current is imbalanced, the circuit still delays the input signal.

Can someone help me to understand the context here in case I missed something?
If it is true that this circuit is just for concept or educational purpose, is there any alternative that can delay both rising and falling edge?

View attachment 181640

What is your supervisor suggesting you use them? This is one of the more common architectures I’ve seen anyways. The one thing to watch here is going from the “slow zone” back to the “fast zone”. If you’re going for a very slow delay think milliseconds, you will have a lot of contention on M8/M7 which will drive up average power.

Also, I think the current conveying from M1 to M2, and then the mirroring from M2 to M6 actually provides better matching because it’s all local to the cell rather than having the biasing somewhere far away. But on the same note, the VCTRL may be better matched brought in as a current from an integration perspective if you only have a few instances of this delay cell.

If you are chaining many of these together, it would be much better to bring the PMOS in as a voltage as well with both the N diode and P diode biases off to the side, less DC current that way.