Delay before assignment.

[munchies]

I'm using VHDL and I want to introduce a delay before assigning two signals to being equal. My thinking is of a switch, that moves from all zeros or null to the wire I want to take the signal from after x amount of clk_cycles. Is this possible? My issue is that my design is outputting junk data before all of the correct data propagates through it fully, I want to assign the output to zero or null until the propagation delay is complete. Is this possible?

Thank you for any assistance or discussion.

 

[keremcant]

does your circuit have a sequential part? because it does you can use it to determine when to assign to output.

what you are saying is not useful, as far as I've understood. you are saying for example you have a wire and you want it to have no value for a time(null), and than you will assign a value to it when you want. null value is not possible in hdl. because every wire and register have a random value at reset, since they are actual bistable solid state devices.

what you can do is that for example, have a cycle counter. and say your circuit finishes its calculations after 150 clock cycles. and you can have an output register that is all zeros upto 150 cycle counts. and you can set that output after the 150. cycle. and you can have also have a one bit signal, say "done". and you set this done signal olnly after the assignment to the result register is finished. this way you can tell the next module that this part of the sytem has calculated its output value, and the value is ready to be taken from its output register.

this is the common way to do what you ask for.

hope this helps.

 

[pfaes]

In simulation, you can delay a signal assignment using after, but that is probably not what you want: **broken link removed**

You probably need to create a signal that knows when the junk has flushed through your module, and use that to switch the output on or off. I propose you add something like this to the end of your module:

finalOutput <= computedOutput when computationReady
  else (others => '0');

 

[munchies]

Okay thank you for that.

I know what I want to base it on, so I want to use something like

IF (Fire'event AND Fire = '1') THEN
......
ComputationReady = '1';

How do I then set the delay I want? In this case it's 4 cycles. I assume using any timing is useless outside of simulation. So I need something like:

wait 8*clk'event

or something like that??

 

[TrickyDicky]

dont use the first idea - you're creating a clock that will cause you all sorts of timing problems.

Best just to set up a counter and wait till it reaches a certain value.

 

[pfaes]

Don't trigger on a rising edge of "fire", that way, you would use "fire" as a new clock, instead of a control signal.

Instead, check for the old value and compare to the new value. Then start counting 4 clock cycles.
Counting 4 clock cycles can be done by shifting the values in a shift register, or by creating a state machine with a counter. Let's do the shift register here:
Assuming declarations like these:

  signal fire,fired,active  : std_logic;
  signal counting: std_logic_vector (4 downto 0);

you something similar to this in your synchronous process:

if rising_edge(clk) then
  if fired ='0' and fire = '1' then 
    -- start counting
    active <= '1';
  end if;
  fired <= fire;

  -- shift register to count for x clocks
  counting(4 downto 0) <= counting (3 downto 0) & active;

  -- don't forget to turn active back to '0' when you're ready!
end if;

 

[FvM]

In a pipelined design, you'll often want to have a DAV (data available) pipeline, that delays a handshake signal together with the data. It not just delays a data ready signal but allows multiple new values to travel the data path at the same time. If the data sink is registering the data according to the DAV signal, you don't need to mask invalid output data.

If the data path is operating sequentially rather than pipelined, e.g. a serial divider unit, a simple DAV counter would be sufficient.