Bidirectional assignment?

[latebird]

Hello,

I have a verilog design and I don't know why it works...

////Top_level////
module tricky_design(port_a,......);

inout [5:0] port_a;          //in & out, physically connects to GPIOs of DSP on my board for read and write.

wire [5:0] a;

assign a = port_a;           // Question here!

////submodule////
sub u1(
.D(a),                        //D is an 'inout' of submodule
...
);
////End of submodule////

endmodule

I think I don't have any other sentences or tri-state logic assigning 'a' to 'port_a', but it is literally working as an 'inout' port, both 'in' and 'out' are functional. The 'assign' should be working one-way, isn't it?
Is it possible that the assignment between two net types will create a 'real' wire, so it works bidirectionally, or, it was optimized by the synthesis tool (synplify pro), I don't know.
Can anyone help?

Thanks!

 

[dave_59]

This certainly would not work in simulation. Do you really need a separate wire a?

 

[latebird]

This certainly would not work in simulation. Do you really need a separate wire a?

Thank you for your reply, Dave.

My board has been working fine with the assign sentence. I don't really need this wire a here, I wonder the assign is not strictly from RHS to LHS in this 'inout 'case. If it is, the 'inout' should be working as an 'input' only.

I did map D to port_a, my submodule 'inout' connects directly to the pins, it works the same way.

//------------------------------------------------------------------
//Code:
////Top_level////
module tricky_design(port_a,......);
inout [5:0] port_a;
//wire [5:0] a;
//assign a = port_a;     
 
////submodule////
sub u1(
.D(port_a), //D is an 'inout' of submodule
...
);
////End of submodule////

endmodule
//-----------------------------------------------------------------

[Moderator action: added CODE tags]

 

[FvM]

My board has been working fine with the assign sentence.

Does module sub read and write the inout port? Intel Quartus gives me errors like:
Error (13066): Illegal directional connection from the pin "port_a[0]" to the node "sub:u1|test_in"

Even if you don't read from the inout port, sub doesn't seem to be able to drive top port_a, as expectable according to the HDL description.

If your synthesis is producing different behavior, it's not according to language specification.

 

[ads-ee]

I've found Synplify Pro will synthesize code that violates the language specification. I've noticed this on old code that was never simulated and it synthesizes fine but Modelsim reports an error when trying to run a simulation.

 

[latebird]

Does module sub read and write the inout port? Intel Quartus gives me errors like:
Error (13066): Illegal directional connection from the pin "port_a[0]" to the node "sub:u1|test_in"

Even if you don't read from the inout port, sub doesn't seem to be able to drive top port_a, as expectable according to the HDL description.

If your synthesis is producing different behavior, it's not according to language specification.

Hi, it does read and write, and I guess it is the synthesis behavior. I don't try it on Quartus, but my design didn't pass the Lattice LSE. Thank you for your reply.

 

[latebird]

I've found Synplify Pro will synthesize code that violates the language specification. I've noticed this on old code that was never simulated and it synthesizes fine but Modelsim reports an error when trying to run a simulation.

Thanks for telling me your findings, I don't know if my codes passed Synplify Pro a good or bad thing. It helps implement my design faster but it also hides some of my language specification problems at the same time. Lol.