Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

DDR3 Signal Integrity Simulation

Status
Not open for further replies.

Harald_Broth

Newbie level 1
Joined
Sep 27, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,289
Hi,

I am a newbie to PCB signal integrity analysis. I have hyperlynx 7.5 n want to perform SI analysis. Kindly let me know how to do pre n post layout simulations, timing budget etc....all parameters
 

TraceRouter

Full Member level 2
Joined
Aug 2, 2005
Messages
142
Helped
24
Reputation
48
Reaction score
6
Trophy points
1,298
Location
Wichita, KS
Activity points
2,158
You might want to upgrade to version 8.0. from what I hear there are wizards that will help you with pre and post analysis of DDR3 or at least that is what my Mentor SI rep keeps telling me.
 

sudhagar124

Newbie level 4
Joined
Oct 23, 2010
Messages
5
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Activity points
1,321
You might want to upgrade to version 8.0. from what I hear there are wizards that will help you with pre and post analysis of DDR3 or at least that is what my Mentor SI rep keeps telling me.

Hi All,

By this time i guess both of you might have become a pro;-) in hyperlynx 8.0,DDRx BAtch simulation.:-D:razz: Am completely new to DDR simulation ,am going to do post layout,with a "similar":-| IBIS model of the DDR SDRAM.

1.Can you help me out on how to assign values to LOT :x of parameters involved in simulation.
2.Also can you suggest some ID's of vendor from where i can getdesired IBIS model of ddr and sd cards.Since i have to do simulation for both.8-O

TIA:)
Sudhagar
 

sudhagar124

Newbie level 4
Joined
Oct 23, 2010
Messages
5
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Activity points
1,321
Micron, for DDR.

Thanks marce,i got the IBIS model of ddr.

Am currently doing SI between FPGA and DDR2.Am using hyperlynx 8.0. As am proceeding, while doing for data strobe,am not getting the differential pair on the fpga side,but am getting differential pair on ddr2 side. I have exported from our board file.
Any suggestion.
FPGA-CYCLONE IV to DDR2.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top