DDR3 Signal Integrity Simulation

[Harald_Broth]

Hi,

I am a newbie to PCB signal integrity analysis. I have hyperlynx 7.5 n want to perform SI analysis. Kindly let me know how to do pre n post layout simulations, timing budget etc....all parameters

 

[TraceRouter]

You might want to upgrade to version 8.0. from what I hear there are wizards that will help you with pre and post analysis of DDR3 or at least that is what my Mentor SI rep keeps telling me.

 

[sudhagar124]

You might want to upgrade to version 8.0. from what I hear there are wizards that will help you with pre and post analysis of DDR3 or at least that is what my Mentor SI rep keeps telling me.

Hi All,

By this time i guess both of you might have become a pro;-) in hyperlynx 8.0,DDRx BAtch simulation.:-D:razz: Am completely new to DDR simulation ,am going to do post layout,with a "similar":-| IBIS model of the DDR SDRAM.

1.Can you help me out on how to assign values to LOT :x of parameters involved in simulation.
2.Also can you suggest some ID's of vendor from where i can getdesired IBIS model of ddr and sd cards.Since i have to do simulation for both.8-O

TIA
Sudhagar

 

[marce]

Micron, for DDR.

 

[sudhagar124]

Micron, for DDR.

Thanks marce,i got the IBIS model of ddr.

Am currently doing SI between FPGA and DDR2.Am using hyperlynx 8.0. As am proceeding, while doing for data strobe,am not getting the differential pair on the fpga side,but am getting differential pair on ddr2 side. I have exported from our board file.
Any suggestion.
FPGA-CYCLONE IV to DDR2.