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DDR3 IC's In a VERY Small PCB

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Junior Member level 2
May 28, 2008
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Pasadena, CA
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Hey guys,

I am designing a PCB with an Intel Atom. My mechanical PCB constraint, make my PCB's physical size VERY small...VERY.
One the Atom chip I am using, I MUST use 2GB, in an 8-chip fashion (2Gb, 256M Addr x 8-bits, 4 chips)

I want to place 2 of the IC's on the back, and 2 on the front, and I want the IC's to be exactly on top of eachother.

I have heard SOME companies make RAM IC's thatr has a mirroed footprint...but I can't seem to find this anywhere.

So because of that, I have come to the conclusion that I am missing some sort of a detail with the standard BGA package.

I want to have them right on top of each other, so I can rout the address lines to vias and have it all linked to the IC's with expoxy-filled vias right on the BGA pads.

My questions are:

1) Am I missing something on how these are suppose to to be routed on top of one another?

2) Do companies like Micron actually make mirrored footprints? OR how can I rout there in a VERY small place?

** Any other advice/details would also be helpful.

Thank you,

I know there was mirrored DDR ram packages, I'll check our data sheets.
As to routing DDR on small boards, its a pain. You have no room for length matching etc. It can be done though, it just takes more effort.
Good Luck

I remember I've also looked for mirrored memories a year back but was unlucky.

---------- Post added at 14:56 ---------- Previous post was at 14:49 ----------

Also, please check with your assembler if they can process BGA memories back to back. Some of the assemblers failed to do so. Make sure you comply to the routing checklist provided by Intel. They provide a document to match the lengths in various topologies.


Having a look round, the last time I got reversed memory was in tsop package, not BGA.

I guess increasing number of layers is a must for this case... Check with manufacturers for manufacturing constraint on via size, clearance and trace width. I think your company should expect additional cost for this board with such mechanical constraint.

Hi guys

for the GDDR5 memory you have a mirror function, you need to set some pull-ups and stuff but it can be done :). I think for other type or RAMs you have something similar... there are several things you can do to improve your density, as mentioned above you can increase the layer count but when you put a PTH via you will consume a lot of area, you increase the technology using thinner traces (~3mils) and thinner PTH vias (8mils diameter) or go even further and have some microvias (6mil diameter) there... of course any of these choices comes with a cost penalty been the uvias option the most costly but highly effective :). personally, if you have a very small form factor, I think the micro vias will be the best option the cost increase with each lamination cycle you add, but you fill have a lot of freedom on the routing :), and if is very small the overall cost should be within range (all celluar phones use this type of tehcnologies xD)

I hope this helps

Hi Peter. I believe DDR3 mirroring is a feature supported by controller. This is what I found:
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a “load mode” operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank.
Following pins are swapped when the mirroring is active: A3<->A4, A5<->A6, A7<->A8, BA0<->BA1. Find more info at: DDR3 memory chip mirroring – PCB layout - (FEDEVEL)

Dont forget the board will need to be controlled impedence.

And essentially length matched too.

The basic question posted is to if there are mirrored memory parts available somewhere. It is unfortunate that Memory manufacturers didn't come up with a solution to this problem yet. A lot of designers would love to use it.


One of the problems is the use of BGA chips, for two reasons:
1. It is usually not reccomended to put BGA devices back to back on a PCB.
2. The absence of lead frames and how the die is mounted in the various packages. When devices were in SOIC. TSOP packages you had a lead frame, that would connect the die to the outside world, in a nice orderly fashion (compare the pin locations between soic and BGA devices) and to create a reverse package was easy, you turned the lead frame and die upside down before encapsulation. When dies are mounted in a BGA package you cant do this due to the mounting method, and so it is almost impossible to create a mirrored BGA package.

BGA tears off easily due to heat. Back to back BGA assembly is very hard to achieve with high cost and detail heat profile managing. And you have to consider your layout design also on head conduction in between the layers.
I think if pmtwiss needs to achieve this, you need to discuss with your manufacturers on their ability. The price is high cost.

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