Bias routing my IC's in PCB

[yefj]

Hello , I have tried to implement your advices and the result is shown below.
i have added 0.1uF bypass capacitors near each +`15V -15V trace of every IC.
Also decoupling capacitors where added near the 3 pin.
The problem is that i have many places where i need to supply the outputs of the 3 pin bias.
I know that i need to do polygon pour on both top and buttom layers which whould be GND .
I can route threw the buttom layers (using VIAs) i can route threw top layer.
what is the proper way to supply my IC's with +15 -15 GND?
I have tried to deliver +15 -15 using via's and buttom layers but it looks like a jungle.
If there is some more proper methodical way to do it?

PCB file is attached in the link.

PCB1.PcbDoc

drive.google.com

 

[FvM]

Only a few steps to get it routed.
- add the few missing +/- 15V routes
- ground fill remaining bottom layer area and add vias

 

[D.A.(Tony)Stewart]

Yes it is a jungle.

• Reduce the decoupling cap requirement as there is no need with such low constant currents on Op Amps, but do that for logic IC's.
• Putting all the passives in the same orientation is one method when possible. Then use, say vertical tracks on one side and Horizontal on the other.
• Add Test Points.
• It would be much easier with a Tri or quad-Amp
• Keep outputs away from high impedance Vin + to avoid say 1 pF crosstalk with positive feedback or any stages with Positive Feedback. ( two inverting filters )
• Do you want to make a 4th order filter? Show the logic diagram. Does the design have a balanced input impedance to have good CMRR for a long cable input with common mode noise on it?
• What supply noise do you expect? The load does not appear to create any noise.
• 
  
• Have enough test pins for probes with a common ground or at least vias for a short resister wire pin if you have no proper ones.