sandhya.im said:can u tell me about the schemes of DDR2 terminations?
aps2itm said:Hi Everybody...
Recently I have simulated a DDR2 266 MHz/533 Mbps memory interfaced with Power QUICC processor to analysis following Results that affect signal quality at the receiver for SSTL 18 signaling�
Proper selection of termination value (ODT)
Data Valid Window & Timing margins (Eye Width & Eye High)
Timing Budget calculations (read & write cycle)
Slew Rate
Over-shoot & Under Shoot
Cross talk analysis
If you have any doubt related to DDR2 Memory Interfaces I may help you�.
Hi,
Anyone here working with Hyperlynx? I got few clarifications about the crosstalk analysis on both batch simulation and Line simulation.
1. The crosstalk considered is for Layer to layer or adjacent nets?
2. Can we do crosstalk analysis in Line sim say for Pre-Si analysis. If so how to interpret from the waveforms it generates.
Kindly clarify
---------- Post added at 18:14 ---------- Previous post was at 18:11 ----------
Regarding address Clocking 1T or 2T how can we find that out. Does that depend on the application or perspective of layout person.?
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