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DDR2 Signal Integrity Simulation & Timing Budget calcula

Is it crucial to simulate DDR2 interface…

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techzee

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Shiva,

So when doing Pre-Si analysis, Then how to probe for crosstalk for some of the critical nets.
 

chamarnadh

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Re: ddr2 signal integrity

HI,
Can you explain how we eliminate the ringing, overshoot and under shoot in the following DDR2 device.I am interfacing with MPC8378controller and DDR2 is MT47H128M16.
I am unable to eliminate the ringing.



Please help me.

Thanks in advance

Amarnadh
 

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techzee

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Hi Amarnadh,

From the waveform it looks like the red waveform is the Receiver waveform. For DDR You can try checking it with by enabling ODT. If you can share the topology that you had followed it would be very clear to help you out.
For Eliminating Ringing try adding up series resistor, but By enabling ODT this should solve the problem, anyways share the topology you followed.
 

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chamarnadh

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Hi Amarnadh,

From the waveform it looks like the red waveform is the Receiver waveform. For DDR You can try checking it with by enabling ODT. If you can share the topology that you had followed it would be very clear to help you out.
For Eliminating Ringing try adding up series resistor, but By enabling ODT this should solve the problem, anyways share the topology you followed.
Thank you for your support.

Sorry my english is not good.

When I enabled ODTs signal voltage level is dropping.I will attach those files.
When I add series resistors, still ringing is there. Iam attaching the stack up details what we are following. please go through and suggest.


The models what we are used is MPC8378 for controller from freescale and NT5TU64M16DG for DDR2 from nanya. I was checked for the equivalent DDR2 from Micron also. still the same results are coming.

Thank you for your support.
Amarnadh.
 

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chamarnadh

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Hi Amarnadh,

From the waveform it looks like the red waveform is the Receiver waveform. For DDR You can try checking it with by enabling ODT. If you can share the topology that you had followed it would be very clear to help you out.
For Eliminating Ringing try adding up series resistor, but By enabling ODT this should solve the problem, anyways share the topology you followed.
Thank you for your support.

Sorry my english is not good.

When I enabled ODTs signal voltage level is dropping.I will attach those files.
When I add series resistors, still ringing is there. Iam attaching the stack up details what we are following. please go through and suggest.


The models what we are used is MPC8378 for controller from freescale and NT5TU64M16DG for DDR2 from nanya. I was checked for the equivalent DDR2 from Micron also. still the same results are coming.

Thank you for your support.
Amarnadh.

---------- Post added at 12:49 ---------- Previous post was at 12:45 ----------

Thank you for your support.

Sorry my english is not good.

When I enabled ODTs signal voltage level is dropping.I will attach those files.
When I add series resistors, still ringing is there. Iam attaching the stack up details what we are following. please go through and suggest.


is MPC8378 for controller from freescale and NT5TU64M16DG for DDR2 from nanya. I was checked for the equivalent DDR2 from Micron also. still the same results are coming.

Thank you for your support.
Amarnadh.

Hi Techzee,

I forget to mention, we are simulating with DDR667Mbps for data,address and strobe signals
333 Mhz for clock.

Rgds
Amarnadh
 

techzee

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Hi,

Hey ur welcome, Don bother about English, This is place to support each other.

I need clarification, if DDR speed is 667 Mbps, then u simulate DATA,STROBE and CLOCK at 333MHz is it not? Address will be 333/2MHz. What is the impedance you maintained, I don think am able to view the stack-up details.

You are getting reflections because there is mismatch between driver and receiver. Can you provide your topology as how you connected Driver and Receiver.
 

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chamarnadh

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Hi,

Hey ur welcome, Don bother about English, This is place to support each other.

I need clarification, if DDR speed is 667 Mbps, then u simulate DATA,STROBE and CLOCK at 333MHz is it not? Address will be 333/2MHz. What is the impedance you maintained, I don think am able to view the stack-up details.

You are getting reflections because there is mismatch between driver and receiver. Can you provide your topology as how you connected Driver and Receiver.
Hi,
Thank you for your support.

I attached my stack up now.U r correct data,strobe and clock at 333Mhz. For address is it required to maintain half the clock freq.I will check up that one.
If i am not wrong what u r asking, this is the topology we are following.
The driver to receiver max.length is 1000 mils for clock and 1200 mils for clock and address. We routed group wise, i.e One byte is on 2nd layer another byte is on 4th layer like that we routed.Total we have connected four 1Gb DDR2 ICs beside the controller on the top layer.Total address lines are 16lines common to all four ICs.64 data lines (4x16).one group consists of 8 datalines, one strobe and one mask signal.Like that two groups for ADDRESS.Clock is routed as differential routing.

please go through and suggest.

Rgds
Amarnadh
 

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Hi,

Hey ur welcome, Don bother about English, This is place to support each other.

I need clarification, if DDR speed is 667 Mbps, then u simulate DATA,STROBE and CLOCK at 333MHz is it not? Address will be 333/2MHz. What is the impedance you maintained, I don think am able to view the stack-up details.

You are getting reflections because there is mismatch between driver and receiver. Can you provide your topology as how you connected Driver and Receiver.
HI,

we are using daisy chain topology.
 

techzee

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Hi,

When I walk through the stackup, layer 4 is plane, I don think you can route on plane laye. Check that out. As for the layers 8 and 10 looks good for High speed signals routing, because it has good plane layers on both sides of the signal. It is the best layer to route your DDR signals, but you check that out.
When any signal layers are tightly packed with planes on either side it help in reducing noise effects. Since your DDR is high speed generally L8 and L10 can be used, for breakouts use your outer layers.

For Daisy chain topology, You generally tend to get lot of reflections if the branching point is not matched properly, i.e check for changing the length of transmission lines where it is getting branched, If any of the receivers is showing a lot of distortions try routing that in longest path and others in short path of the daisy. I am sure when u adjust your branching point lengths the effect of ringing and overshoots will be limited.

For overshoots & Undershoots as per the JEDEC standards check the permissible voltage limit, I believe it 0.3V. If that is meeting the standards then it is ok to proceed.

Anyways share your comments on this.

---------- Post added at 03:40 ---------- Previous post was at 03:38 ----------

You can adjust your board thickness at Layer 9 substrate for impedance control
 

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shivapugal

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Hi,

If it is DDR667Mbps, then you must simulate with the following,

data/data mask nets as 667Mhz,

strobe(dqs), clock = 333Mhz

control nets = 333Mhz

address/commnad = 333Mhz if it is IT clocking scheme or 166 for 2T.

For the simulation you must use models from the micron for the memory chip cause you have mentioned the part no as MT47H128M16. The models of the part will be readily available from the micron website. Check the below link for the model.

MT47H128M16HG-25

You don't need to worry about the voltage reduction until it meets the threshold values. let me know if you have doubts in threshold values for logic 1's and 0's.

We can still live with ringing until it wont crosses the overshoot and undershoot values which causes reliability issues, crosstalk and EMI.

Change the address daisy chain routing to the T-Point routing and place the VTT termination at the junction point and make sure the signals from t-junction to all the 4 memory chips are same. You need to run a simulation to find out the maximum trace length from processor to T-junction and from T-junction to the memory chips. It is very simple to do that. This will solve your address/cmd/control issue.

SSTL18 is the standard logic level for the DDR2. Refer the attached JEDEC standard.

The maximum limit for overshoot/undershoot are 2.1 and -0.3V respectively for all the DDR2 signals.

Let me know for more queries.

Thanks
Shiva
 

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chamarnadh

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Hi,

Thank you for detailed analysis from both of you.

Layer 4 is not plane , it is signal layer only . Because of the copper % it is taken as plane and I am using 8layer stack up only. Any how i will check once again.

After some iterations i achieved with out undershoot & overshoot by adding one 10pf cap pull down to gnd at the driver side and and Pull up resistor to Vtt at last DDR2 IC. But my concern is with rise/fall monotonic for dta signals. Because of this my signlas are failing in the simulation report.
I am attaching those signals for your perusal and comment.

Thank you.
Amarnadh
 

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Hi,

If it is DDR667Mbps, then you must simulate with the following,

data/data mask nets as 667Mhz,

strobe(dqs), clock = 333Mhz

control nets = 333Mhz

address/commnad = 333Mhz if it is IT clocking scheme or 166 for 2T.

For the simulation you must use models from the micron for the memory chip cause you have mentioned the part no as MT47H128M16. The models of the part will be readily available from the micron website. Check the below link for the model.

MT47H128M16HG-25

You don't need to worry about the voltage reduction until it meets the threshold values. let me know if you have doubts in threshold values for logic 1's and 0's.

We can still live with ringing until it wont crosses the overshoot and undershoot values which causes reliability issues, crosstalk and EMI.

Change the address daisy chain routing to the T-Point routing and place the VTT termination at the junction point and make sure the signals from t-junction to all the 4 memory chips are same. You need to run a simulation to find out the maximum trace length from processor to T-junction and from T-junction to the memory chips. It is very simple to do that. This will solve your address/cmd/control issue.

SSTL18 is the standard logic level for the DDR2. Refer the attached JEDEC standard.

The maximum limit for overshoot/undershoot are 2.1 and -0.3V respectively for all the DDR2 signals.

Let me know for more queries.

Thanks
Shiva
Hi,

What are the threshold values for the 1s and 0s.
If you observe my data signal wave form the max voltage is less than 1.6v. we are not achieving the full 1.8v (or 1.8-10%of the 1.8 i.e 1.62v).Is it effect the signal during the operation.My doubt is if i am using 75Ohms ODT the amplitude further reduces.

Please clarify.

Amarnadh
 

shivapugal

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Hi Amarnath,

Well you have cleared the overshoot problem by adding VTT termination at the last memory.. I hope the 10pf capacitor will clear the non-monotonicity and causes the signal to rise/fall smoothly, but it do increases the rise/fall time anyhow i think freescale also suggest to implement 10pf capacitance to ground at the driver.

Data and address signals need not to be monotonic all the way. if the non-monotonicity is after the threshold values then it is not a problem for data and address signals. only for the clock and dqs the monotonicity during the rising and falling is important.

From the waveform I understand you are using random bits for the simulation. can you use pulse and see the waveform at the receiver for monotonicity?

Since you are using hyperlynx for the analysis I believe you can set the maximum overshoot levels in the settings before the simulation.

The threshold levels for the SSTL logic is given in the JEDEC standard which i attached in my last reply. The same will be given in the micron datasheet.
The threshold levels are measured when it cross VIH(AC) and VIL(AC).

If the signal crosses VIH(AC) the receiver detects the signal as logic 1 and when it goes below the VIL(AC) the receiver interprets the signals as logic 0. The inbetween state is called tristate. Even interesting the threshold values will be maintained until it goes below and above of VIH(DC) and VIL(DC).

VIH(AC) = 1.15V, VIL(AC) = 0.65V, VIH(DC) = 1.025 VIL(DC) = 0.775V. So your waveform seems to ok with the threshold levels. It doesn't need to go all the way to 1.8V.

Thanks
Sivalingam
 

techzee

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Hi,
Wat Sivalingam suggests is a good idea. Your signals are well cleared of the problem.
Run the waveform with duty cycle 50% and check it for receiver.
Even though the layer 4 seems signal, it is better to route in inner signal layers both 8 and 10 has reference planes on both sides.
For the non-monotonic edges still if u feel troubled about it, you would have done timing analysis right?
Check the delay with your analysis and I don think it would become a problem.
 

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Hi,
Wat Sivalingam suggests is a good idea. Your signals are well cleared of the problem.
Run the waveform with duty cycle 50% and check it for receiver.
Even though the layer 4 seems signal, it is better to route in inner signal layers both 8 and 10 has reference planes on both sides.
For the non-monotonic edges still if u feel troubled about it, you would have done timing analysis right?
Check the delay with your analysis and I don think it would become a problem.
Thank you ,

I achieved some good output after few iterations.

THANK YOU FOR YOUR SUPPORT.

Amarnadh
 

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Re: ddr2 signal integrity

Hi Everybody...

Recently I have simulated a DDR2 266 MHz/533 Mbps memory interfaced with Power QUICC processor to analysis following Results that affect signal quality at the receiver for SSTL 18 signaling…

Proper selection of termination value (ODT)
Data Valid Window & Timing margins (Eye Width & Eye High)
Timing Budget calculations (read & write cycle)
Slew Rate
Over-shoot & Under Shoot
Cross talk analysis

If you have any doubt related to DDR2 Memory Interfaces I may help you….
Hello I have few doubts in simulating DDR2SDRAM in Hyperlynx. Could you please help me with eyemask preperations?
Ravi
 

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