DDR memory interconnect

[shaiko]

Hello,

Leaving signal integrity issues aside - is it functionally possible to connect DDR3 memory to several masters over a single parallel bus?

 

[pbernardi]

Hi,

I don't think you can leave the signal integrity issues aside in DDR3, it would affect your circuit functionality.

Also, if these "several masters" you are talking about are processors, then no. As each processor think he is the master you would have collisions, and DDR3 is not prepared for this situation.

If your "several masters" are FPGAs, for example, you might try to implement some protocol to avoid collision, but it surely would cost logic (or better, latency inside FPGA) and slow down your DDR3 frequency. So, perhaps it might be possible, but I don't think it is wise.