DDR is burst oriented already -- a read or write will access multiple addresses. For reads, the extra data is ignored. For writes, the write mask signals are used. The specifics of the burst are somewhat configurable on the IC, but some modes may not be supported by the memory core. This means you'll get 128b (or more for BL8/BL16) from each read/write command anyway.
However, accesses that are not aligned to burst-size boundaries will be treated specially as shown in the DDR datasheet. Eg, writing to address 1 will result in accesses to address 1, 2, 3, 0. (for BL4). The memory controller you use may already have logic built in to perform the extra read/write to get the expected behavior from the user perspective.