DDR Memory Address Granularity

[shaiko]

Suppose we have a DDR memory chip with a 32 bit data bus.
How many bits will be stored in each memory address?
I.E:
Does it store all 32 bits in a single memory address? Or does it store it into 4 consecutive addresses (one byte in each address)?

 

[TrickyDicky]

Why any chips, the convention is that the address bus is the word address, so each address holds the whole word (anything else would be wasted pins)
It's just CPUs that make life complicated by doing byte addressing.

 

[FvM]

If you answer the question from the ram chip perspective, there will be e.g. 4 byte-wide RAM chips that hold the 32 bit data and get the same row and column address. In so far the data is stored in one address.

But the cpu data model usually represents the data as four bytes with consecutive addresses.

Consider that the two less significant address bits are mapped to RAM byte enable signals.

 

[shaiko]

Thanks,
Another question.

Suppose the clock frequency of our FPGA's DDR controller is 400MHz.
400 * 2 ( double data rate ) = 800MB/s.
Working on the FPGA fabric with a 800MHz clock is out of the question.
So we scale down our clock by a factor of 4 to something more reasonable: 200MHz.
This forces us to scale up the data width by 4 to: 32*4 = 128 bits.

So now, every memory access will address 4 locations at ones - correct?

 

[vGoodtimes]

DDR is burst oriented already -- a read or write will access multiple addresses. For reads, the extra data is ignored. For writes, the write mask signals are used. The specifics of the burst are somewhat configurable on the IC, but some modes may not be supported by the memory core. This means you'll get 128b (or more for BL8/BL16) from each read/write command anyway.

However, accesses that are not aligned to burst-size boundaries will be treated specially as shown in the DDR datasheet. Eg, writing to address 1 will result in accesses to address 1, 2, 3, 0. (for BL4). The memory controller you use may already have logic built in to perform the extra read/write to get the expected behavior from the user perspective.

 

[shaiko]

Can you please suggest a tutorial with simple reference design that implements a DDR2 (or 3) controller on an FPGA ?

 

[shaiko]

FvM,

Consider that the two less significant address bits are mapped to RAM byte enable signals.

So if we have a memory chip with a 32 bit wide address bus.
The CPU internal address bus will actually be 34 bits wide? The 2 least significant address bits are internal to the CPU and have no effect on the data being strobed?

 

[TrickyDicky]

That is assuming the address from the CPU is a byte address (which it usually is).