[SOLVED] DCM /PLL/ Clock multiplier and rise & fall time

[Pharmboy]

Hello, I couldn't find any information on this so I'm asking here.

When using a DCM / digital PLL to multiply up a clock does the rise/fall time of the clock limit the max frequency of the output clock in any way?

More specifically will the rise/fall of the output clock be identical to the input clock or will it be different? Say you use a PLL to double the input clock, will the rise/fall time be say.. cut in half or stay the same? If it stays the same, and both are at 4ns, wouldnt the max frequency you can pump out be f = 1/(2*4ns) = 125MHz otherwise the output clock will fail to reach the same high voltage level as the input clock?

Hope some of you guys know this, I know I could probly know this if I took the time to learn about the internal workings of DCM/PLL, but right know I dont have the time , I just need it as a 'black box'.
Thanks in advance for any reply..

 

[dick_freebird]

Output rise/fall will depend on output buffer drive strength and
loading. Input rise/fall will contribute to jitter / PN, the slope
there and the input linear region width determine your voltage
noise to time noise (jitter) transform. The two are not specifically
related if you have any significant stage-count and are not up
against the speed limitations of the gates.

The input (reference) clock does not generate the output, it
is what the VCO / NCO / WETFCO is slaved to but the signal
that is slaved, is generated by blocks other than the ref clk
path to phase comparator.

 

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Beyond what dick_freebird has already mentioned (generically for PLLs/MMCMs).

Xilinx's PLL/MMCM uses counters at the output to generate all the clocks. This divides down the VCO frequency, which is the limiting factor in the maximum clock frequency of the PLL/MMCM outputs.

The DCM is slightly different as it does this digitally with a series of digital delay line taps, which phase shift the input clock, and can be used to produce a 2x and 2x 180 degree versions of the input clock. All the clocks from the DCM are output through a buffer stage and then the global buffers. The DFS of the DCM is basically an NCO implementation that uses the fine resolution of the delay line. As you can easily see the DCM is very limited in what it can do. It is also not at all good at cleaning up input clock jitter, in fact it will just pass all the jitter (while adding more) to the output clocks.

 

[Pharmboy]

Thank you for your reply.
What about the commercial PLL ICs out there?
I'm specifically interested if it's possible to get a 3.5 GHz clock for the AD9914 DDS chip from AD.
Can't really find any clock oscillators to run at this frequency so guess I need some kind of PLL? Im really way out of my skill level and money funds here so not really gonna build this something out of this, I can just say its for a short part of a text im doing for my undergrad. Again, ty in advance for replies..

 

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There is a discussion about driving that part in the following message board for Analog Devices.
https://ez.analog.com/message/73296