srinivasansreedharan
Junior Member level 3
Hi,
I would like to know what these commands mean internally during synthesis of a design in Cadence Design Compiler.
1. set_balance_registers <true or false> (What are balance registers and their significance)
2. set_max_area <value> -ignore_tns (What does tns mean?)
I would like to know what these commands mean internally during synthesis of a design in Cadence Design Compiler.
1. set_balance_registers <true or false> (What are balance registers and their significance)
2. set_max_area <value> -ignore_tns (What does tns mean?)