DC Synthesis - Clarification on certain commands

[srinivasansreedharan]

Hi,
I would like to know what these commands mean internally during synthesis of a design in Cadence Design Compiler.

1. set_balance_registers <true or false> (What are balance registers and their significance)
2. set_max_area <value> -ignore_tns (What does tns mean?)

 

[rca]

tns: total negative slack

 

[gliss]

Design Compiler is made by Synopsys, not Cadence.

set_balance_registers tells Design Compiler that it can try to optimize timing for the design by moving registers around. Setting this to false disables that capability.

 

[uxarkirnamak]

set_max_area tells Design Compiler to optimize design area to fit to that value. For instance, if you enter

set_max_area 100

DC will try to optimize your design and fit it into 100 <library area units>. If it cannot accomplish this task, DC reports violation, which you can see typing

report_constraint -all_violators

The -ignore_tns tells DC to ignore TNS (total negative slack) while optimizing area. The point is that timing constraints have higher priority over area constraints and at first DC tries to meet the timing constraints (TNS). -ignore_tns attribute tells DC to ignore the total negative slack (BUT NOT WORST NEGATIVE SLACK!!!!!!!) while optimizing for area!