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Do you mean a small offset or a large offset that hurts your ADC range?
Most digital receivers have an IF bandpass filter (to provide the required receiver selectivity), and that also removes DC offset.
I'm intereseted in the DC Offset removal of the timing recovery. Generally it is done as follows: The differerence in the input sample and the accucmulator of the one/zero symbols is given to the DAC and is given to the AGC and is compred with the incoming signal and the output of the AGC is given to the ADC.
By objective is to remove the DAC and AGC and correct the DC by using FPGA and ADC only. Is there is any method????