DAC resolution and substrate noise

[sharkies]

Let's consider a 1.0V supply current-steering 10-bit DAC in 90nm.
1LSB will be approximately as small as 1mV.
Now, if the current-steering DAC is driving an on-chip resistor, then the voltage across this resistor should change by 1mV when the input code changes by 1LSB.
If we consider a PMOS current cell for the DAC, the DAC resistor is connected to the current cell on one side, and the analogGround on the other side.
However, the analogGround will inevitably fluctuate more than 1mV due to substrate noise etc.
How do people get around this problem? Does making the resistor off-chip help? since this way the resistor is connected to a more quiet ground reference? I am quite confused here..

 

[erikl]

... the analogGround will inevitably fluctuate more than 1mV due to substrate noise etc.

Hey sharkies,
how could people design & successfully create 10b-, 12b-, and even 14b-converters on std. CMOS processes?

• minimize substrate noise by screening the noise sources as good as possible
• using EPI wafers
• screening the sensible parts of the converter as good as possible: guardRing(s), n-well, SOI (ok, the latter is not a std. CMOS process)
• extra clean analog GND & PWR supply

Not quite simple at ≥ 12bit resolution, perhaps 1 or 2 redesigns should be envisaged (also concerning the necessary layout symmetry), but finally it will work!