D-Flip Flop pos-edge triggered, lo-async-clear/set, q-only

[urimi]

Hi friends,

how to design a d flip flop with positive egde triggered, low asyncronous clear and set and q only using cmos, could you please give the suggesions for implementation.

thank you in advance,

Regards,
urimi

 

[kenambo]

Hi,

There is many topologies are available for FF ..
In simple, Two latches are combined to give you a FF of your choice...
Refer "CMOS circuit Design, layout and simulation" by JAcob Baker or search the net..

Thanks,...

 

[dick_freebird]

An old RCA CMOS databook is a handy friend to have.
Back when real men published their schematics without
fear or greed.

 

[urimi]

Yes many topologies are avalable.
but my target is to reduse the power comsumption.

Thank you,..

- - - Updated - - -

Thank you friend,........

 

[erikl]

Here's a functional schematic (from Artisan):

 

[urimi]

Thank you............erikl

due to this area is more ........i have to reduce the area also for high speed.

Regards,
urimi