[SOLVED] D Flip Flop frequency divider

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Hi all,

I'm using a transmission gate base DFF to build a simple frequency divider. It worked, but I'm getting some weird waveform at some intermediate nodes and the power consumption is high too (11uW). Could anyone kind enough to provide some insights on this problem.

Here is the testbench, I'm using 1.8V VDD and 100kHz clock.


Here is the DFF sch:


Here is the waveform, you can see I have some weird staircase like waves in some nodes.

 

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well, the problem is that you connected pmos bulk to its drain I think.
usually transmission gate bulks are connected to VSS (nmos) and VDD (pmos), otherwise you cannot really open them. connect m0 bulk to VDD.
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how the transmission gates look like? It seems I10 is not closed and/or I5 provides strong DC output current somehow which raise node A's potential
 

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Hi,

I´m not familiar with IC design.
But the diagram looks like nodes A, B and C are short circuited somehow.

Also from the DFF schematic it looks like at least nodes A and C can be (are) driven by 2 sources. This calls for trouble.

Klaus
 

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frankrose said:
how the transmission gates look like? It seems I10 is not closed and/or I5 provides strong DC output current somehow which raise node A's potential
Click to expand...


This is my transmission gate, I'm using tsmc 65nm
 

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well, the problem is that you connected pmos bulk to its drain I think.
usually transmission gate bulks are connected to VSS (nmos) and VDD (pmos), otherwise you cannot really open them. connect m0 bulk to VDD.
 

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Solution
frankrose said:
well, the problem is that you connected pmos bulk to its drain I think.
usually transmission gate bulks are connected to VSS (nmos) and VDD (pmos), otherwise you cannot really open them. connect m0 bulk to VDD.
Click to expand...
Thanks, that solves the problem!
 
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