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Input stage in a reduced input swing sense amplifier flip flop

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May 18, 2014
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In a sense amplifier based flip flop as shown in the figure, if the data input (D) and clock input (Clk) have Vdd/2 (half the supply voltage) swing, then will it necessitate to use complementary structure instead of the shown structure (i.e. PMOS input pair and PMOS tail transistor, along with NOR based SR latch)?



I'm afraid to say I can't answer your question (without spending possibly hours working out what happens with each combination of inputs). Why not simulate it and see?

Seems a bit "busy". It looks mostly like a simple clocked
comparator. I think you might benefir by breaking it up and
putting it back together once you understand that the
comparator core is working correctly (like, does the bit
you are sensing really provide the complementary D. /D
inputs, or are you using a mid-range static input for one
and just looking for gain, and if to do you have the Vref
properly positioned?).

A shorted inverter, where you release the short just before
attaching to the sense line, might be simpler and adequate
if you have a single ended bit signal. You can get more gain
from a series chain if you like.


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By adding a pull-up/down resistor at a digital input, you can persuade it to respond to non-standard volt levels.

Example, inverter changes state in response to weak signal:

pull-up resistor allows invert-gate to respond to 1V signal.png

--- Updated ---

Resistors can add hysteresis (via positive feedback) such that a buffer-gate by itself becomes a memory cell.

Example, potentiometer selects between 0 and +5v. By pressing momentary switch, the AND gate stores a high or low. Not too different from RS flip-flop.

pot sends 0-5V range switch stores hi or lo hystersis AND gate.png
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