Critical path has changed after I have changed timing constraints...Why?

[dada999]

Dear all,

Thanks in advance for your help!

I have synthesized my design in synopsys design vision, at first I create the clock to 10 ns, and the timing report showed that slack is 0, and the critical path is one bigger multiplier. Then I changed the clock to 4ns, this time it took me more time to synthesize my design(2 hours), then I still got 0 slack, but the critical path has changed to a another smaller multiplier. I really dont know what happened. It seems the first result about critical path is correct, but how to explain the second result?

Another problem is if I want to find out how fast my design can run, what should I do? Should I just set a very small clock cycle, and see the slack?

 

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Another problem is if I want to find out how fast my design can run, what should I do? Should I just set a very small clock cycle, and see the slack?

This is a backward way of looking at designing something.

If someone wants a design to run at 250 MHz they don't just design something and then see how fast it can run by using a 1 ns clock period. You instead use the correct period constraint with jitter margin for a 250 MHz clock. You also keep in mind that you are trying to meet a 250 MHz constraint so you don't attempt to code a 128x128-bit multiplier in 1 clock cycle or other such silliness.

 

[Dar89]

Dear all,

Thanks in advance for your help!

I have synthesized my design in synopsys design vision, at first I create the clock to 10 ns, and the timing report showed that slack is 0, and the critical path is one bigger multiplier. Then I changed the clock to 4ns, this time it took me more time to synthesize my design(2 hours), then I still got 0 slack, but the critical path has changed to a another smaller multiplier. I really dont know what happened. It seems the first result about critical path is correct, but how to explain the second result?

Probably at 10ns the constraint was not so tight, so the synthesizer closed the timing without making significant trasformations. Instead, imposing a constraint of 4ns, has required a stronger effort to close timing. Therefore the synthesizer has probably made architectural trasformations to your design, therefore the critical path is changed.

 

[dada999]

This is a backward way of looking at designing something.

If someone wants a design to run at 250 MHz they don't just design something and then see how fast it can run by using a 1 ns clock period. You instead use the correct period constraint with jitter margin for a 250 MHz clock. You also keep in mind that you are trying to meet a 250 MHz constraint so you don't attempt to code a 128x128-bit multiplier in 1 clock cycle or other such silliness.

Thanks for your reply!
I think I have understood the result. Another question is, after I have synthesized my design, can synopsys dc tell me how much power it will consume under the clock frequency of 50MHz? I dont need the data by using report power since this power is under the extreme tight clock, I need the power when it runs at a slow frequency.

 

[dada999]

Thanks very much. I also found that the area is much larger when the clock is set very tight, is this normal during synthesis?