Google for "Verilog PLI" to find answers. But why would you want that today? Given that SV (and E,OpenVera) has good OOP and abstraction modeling capabilities - usage of CPP for Verif is kind of going down. Anyway take a look at www.trusster.com for a methodology around C++ based testbenches.
cpp can only intract with hdl simulator using PLIs. So if you write a cpp testcase then you must use PLI to apply stimulus generated in cpp testcase to hdl simulator.
Kr,
Avi http://www.vlsiip.com