cpp testcase and verilog code

[shiv_emf]

Hi
suppose v write testcase in cpp. How does it apply vectors to verilog module ?

 

[deepu_s_s]

i think we may pass the vectors through functions or tasks in test bench.

correct me if i am wrong

 

[aji_vlsi]

Hi
suppose v write testcase in cpp. How does it apply vectors to verilog module ?

Google for "Verilog PLI" to find answers. But why would you want that today? Given that SV (and E,OpenVera) has good OOP and abstraction modeling capabilities - usage of CPP for Verif is kind of going down. Anyway take a look at www.trusster.com for a methodology around C++ based testbenches.

Regards
Ajeetha, CVC
www.noveldv.com

 

[avimit]

cpp can only intract with hdl simulator using PLIs. So if you write a cpp testcase then you must use PLI to apply stimulus generated in cpp testcase to hdl simulator.
Kr,
Avi
http://www.vlsiip.com