p11
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Code:
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-- Company:
-- Engineer:
--
-- Create Date: 17:38:49 05/13/2015
-- Design Name:
-- Module Name: COUNTLED - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity COUNTLED is
Port ( CLK : in STD_LOGIC;
X : in std_logic_vector(1 DOWNTO 0);
Y : out std_logic_vector(1 DOWNTO 0));
end COUNTLED;
architecture Behavioral of COUNTLED is
begin
process(X,clk)
VARIABLE COUNT :integer := 04;
variable INT : std_logic_vector(1 DOWNTO 0);
variable b : std_logic :='1';
variable c: std_logic;
variable z : std_logic_vector (1 downto 0);
BEGIN
int (1 DOWNTO 0):= x (1 DOWNTO 0);
L1: loop
if (rising_edge (clk)) then
z(0) := int(0) xor b;
c := int(0) and b;
y(0) <= z(0);
z(1):= (c xor int(1));
y(1) <= z(1);
int (0) := z(0);
int (1) := z(1);
else
end if ;
COUNT :=COUNT -1;
EXIT L1 WHEN COUNT =0 ;
END LOOP L1;
end process;
end Behavioral;
here i have designed a 2 bit counter that gives 00,01,10,11 if initialized from outside (input port of fpga) as 00.here , the loop continues unless it counts 4 times , after which the loop ends . here for every rising edge of clock the count begins . I am new in this fiels , please help and let me know if there is any mistake in my desi