counter using vhdl and implementation in fpga

[p11]

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:38:49 05/13/2015 
-- Design Name: 
-- Module Name:    COUNTLED - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity COUNTLED is
    Port ( CLK : in  STD_LOGIC;
	        X : in  std_logic_vector(1 DOWNTO 0);
           Y : out  std_logic_vector(1 DOWNTO 0));
end COUNTLED;

architecture Behavioral of COUNTLED is  


begin
process(X,clk)
  
 
  VARIABLE COUNT :integer := 04;
  
  variable INT : std_logic_vector(1 DOWNTO 0);
  
  variable b : std_logic :='1';
  variable c: std_logic;
  variable z : std_logic_vector (1 downto 0);
  
  
  BEGIN
    int (1 DOWNTO 0):= x (1 DOWNTO 0);
  
  L1: loop
  
  if  (rising_edge (clk)) then 
  
  z(0) := int(0) xor b;
  c := int(0) and  b;
  
  y(0) <=  z(0);
  
  z(1):= (c xor int(1));
  
  y(1) <= z(1);
  
 int (0) := z(0);
 
 int (1) := z(1);
 else 
 
 end if ;
  
COUNT :=COUNT -1;
EXIT L1 WHEN COUNT =0 ;
	 
	 
END LOOP L1;
		 
  
  end process;
 
       
end Behavioral;

here i have designed a 2 bit counter that gives 00,01,10,11 if initialized from outside (input port of fpga) as 00.here , the loop continues unless it counts 4 times , after which the loop ends . here for every rising edge of clock the count begins . I am new in this fiels , please help and let me know if there is any mistake in my desi

 

[std_match]

You are on the wrong track. You need a VHDL text book and a simulator. Start with working examples and then try to modify them.
Don't use variables until you have a better understanding.

Get a text book that uses numeric_std and stay away from the non-IEEE packages std_logic_arith, std_logic_unsigned etc.

 

[lucbra]

The problem is that someone might find this code using google and start using it.

Isn't there a possibility to scrap this code?

 

[andre_luis]

The question seems quite trivial, being almost a behavioral description of what you want, however the code above uses a structural implementation which use too much lines of code and is harder to debug.

 

[TrickyDicky]

Please, Read a VHDL book and/or tutorial.

 

[vGoodtimes]

Curiously, I decided to just google this subject "vhdl counter example".

link 1: ftp://www.cs.uregina.ca/pub/class/301/counter/lecture.html
Uses "after 50ns", although this will synthesize correctly, well other than the lack of a conversion to slv.

link 2: **broken link removed**
This is how someone might actually write the code. Everyone might not agree on the style, but it is at least believable as something written for synthesis.

**broken link removed**
This actually reinvents "rising_edge(clk)" using variables.

Somehow the worst code examples are getting pushed to the top of google search.

 

[ads-ee]

link 2: **broken link removed**
This is how someone might actually write the code. Everyone might not agree on the style, but it is at least believable as something written for synthesis.

It's using the synopsys packages, so right there is a knock against it qualifying as "good" example code. ;-)

That other link to Southern Illinois university makes me wonder what they are trying to teach the engineering students taking the class that is using that as a counter example. 8-O

Somehow the worst code examples are getting pushed to the top of google search.

I guess this shows how Google has transitioned from doing no evil to doing evil on a regular basis. ;-)

My third link was the following:
https://www.asic-world.com/examples/vhdl/up_counter_with_load.htmland we can blame A. Pham for not using the numeric_std package. though they did use rising_edge(clk) instead of the usual clk'event and clk = '1' stuff.