nactive region
Generally speaking, If you are using a kit you will find a standard cell for your transistor ready to be used..
If you are making own layout, then here are the steps:
1. First draw the well, for NMOS on single well process then no well exists. If PMOS use NWELL, if NMOS on triple well technology use PWELL
2. Then you need to define the OD "Oxide definision", if you can find this layer make it in place where your transistor will be put. if you cant find it go on.
3. Now Define the diffusion for the Source and drain, the width of this region is W of transistor, and the length is technology dependent.
4. Add the poly to make the gate, the width of the poly region is L of the transistor
5. Add the Diff/M1 contact and M1 to connect S and D areas.
6. Finally if using NWELL and PWELL you need define well contact.
7. Vias are only needed for higher metal layers
Good Luck