corner analysis and models

[dipanjan]

hi can anyone tell me how to set up corner analysis and monte carlo analysis??
why is it imp??

anyone got a manual of sorts or reading material on this??i will greatly appreciate any help

i saw that there are various models of the transistors fast fast fast slow typical....
how are we differentiating the performance of a transistor ....on what basis or rather due to what does transistors become fast or slow...can someone explain please?

looking forward to your help

 

[Teddy]

The typical models cover transistors which are done in optimal way - you can say they are ideal.
Corners like fast fast etc cover usually +/-3sigma range from the typical and are supposed to make sure that your design will work when there is a shift in manufacturing process.
Also it covers use of different fabs (if you use UMC or TSMC your chip could be done in any of ther x fabs unless you specify).
Monte carlo just runs the gausian distribution for some basic parameters of the devices like Vt, L, W etc. and if the models are setup correctly corner models will be at the end of the monte carlo distribution.
What can change? If you have ideal process as you read in books then there would be no need for ie mismatch. In real life nothing is ideal so if your diffusion time is slightly longer, the day before the fab personell had few many you can change Vt or have slight variation of the L or W. It is all statistical stuff an if you want to understand more just google it up.
Should you run the corners? Not if you are highly self confident or don't care(like if it is a school project). Yes if you want to keep your job.
I also recommend to open the model file in text editor and compare Typical model to Fast and Slow - right there you will see what is changed.
Then if you have access to any fab data get the wafer probe data and look at it (I mean process test structures probe not your device!) there you can see lot to lot how things are changing.
It is actually really cool to see how much things vary and yet we still can make ICs!

 

[dipanjan]

well i was trying to understand what ff or ss means..... after reading your post it seems it refers to doping conc...am i right...like due to process variations if the doping varies and i get a transistor with greater conc...thn how it will act...

thank you