bobdyadada
Newbie

Hi everyone,
I am VLSI Design student, and for this semester, I need to complete a mini project. I'm really interested in designing and analyzing Phase-Locked Loops. I have experience with Verilog, Ngspice, and will be using Cadence Virtuoso for the design and simulations.
I’m looking for suggestions on specific problems or aspects of PLLs that I could focus on for my project. Since the project needs to be completed within the next month, I’d appreciate ideas for manageable yet impactful problems.
If anyone has worked on similar projects or has suggestions for a problem statement, I’d really appreciate your input. Thanks
in advance!
I am VLSI Design student, and for this semester, I need to complete a mini project. I'm really interested in designing and analyzing Phase-Locked Loops. I have experience with Verilog, Ngspice, and will be using Cadence Virtuoso for the design and simulations.
I’m looking for suggestions on specific problems or aspects of PLLs that I could focus on for my project. Since the project needs to be completed within the next month, I’d appreciate ideas for manageable yet impactful problems.
If anyone has worked on similar projects or has suggestions for a problem statement, I’d really appreciate your input. Thanks
in advance!