Sample-and-hold Amplifier

[theguardian2001]

Hello everyone,
I am trying to implement sample-and-hold amplifier and I am getting the results, which I am not sure how to interpret. The first of the attached figures is the one I am getting by sampling the input signal on a sampling capacitor and that is similar to the figure one can see in textbooks when it comes to S/H. The second one is what I am getting by testing the circuit you can see in attachments using ideal switches and an ideal opamp. The last one is the same test setup but with bootstrapped switches and a "real" opamp. The question is:how should I modify the circuit such that the sampled signal does not "swing" so much,ie making it look similar to the first of the attached figures? I can also see the offset on the last figure, which probably tells that I have to use a fully-differential circuit with CMFB inside the opamp.

 

[barry]

1. Your plots are difficult to see. zoom in a lot more so we can see the details.
2. You don’t show the switch timing.
3. That’s no S/H circuit that I’ve ever seen. But maybe that’s just me.

 

[dick_freebird]

Real switches have real capacitances and inject charge on switching edges. You can balance Cs, phase and soften edges for some improvement but sampled data does not care about how crappy things look, so long as they've settled clean by next sample clock.

 

[D.A.(Tony)Stewart]

If you can cite the original schematic image and parts used to simulate, there will be obvious differences we would rather not guess. A differential sample and hold switches will reduce charge injection from switching capacitance.

The original plot uses about 10 samples per sine so it is easier to see and better to understand the timing as well. There must be specs for capture time, release, hold and release time.
The capacitance must not have dielectric absorption and the slew rate is limited by some Rs and RC with some leakage currents,

 

[theguardian2001]

1. Your plots are difficult to see. zoom in a lot more so we can see the details.
2. You don’t show the switch timing.
3. That’s no S/H circuit that I’ve ever seen. But maybe that’s just me.

You are right, here comes the timing waveform. That might be not entirely clear from the figure, so I would write explicitly that phi1 is high for the first 5ns, phi2 is delayed by 0.1ns, and both of them stay high for 4ns; and phi3 shoots up at 6ns and stays high for 3ns. phi1/2 and phi3 do not overlap.
The second figure shows a zoomed-in version of the opamp's output using bootstrapped switches and two-stage folded cascode amplifier.

--- Updated Feb 20, 2025 ---

Real switches have real capacitances and inject charge on switching edges. You can balance Cs, phase and soften edges for some improvement but sampled data does not care about how crappy things look, so long as they've settled clean by next sample clock.

I am also guessing that something should be wrong with the switches and their timing. The circuit I have attached is taken from Baker "Mixed Signal Circuit Design", when I started to face difficulties with timing, I have looked up the LTspice files the author has made - the timing is taking from there in order to verify the functionality.

--- Updated Feb 20, 2025 ---

If you can cite the original schematic image and parts used to simulate, there will be obvious differences we would rather not guess. A differential sample and hold switches will reduce charge injection from switching capacitance.

The original plot uses about 10 samples per sine so it is easier to see and better to understand the timing as well. There must be specs for capture time, release, hold and release time.
The capacitance must not have dielectric absorption and the slew rate is limited by some Rs and RC with some leakage currents,

As I have mentioned, the "ideal" figures are obtained using "ideal" switches from NGspice library with 1G off-resistance and 0.1 on-res. I have also used vcvs as an ideal opamp model. You are completely right saying 10 samples per sine, the sine frequency in the first plot was set to 10MHz while sampling clock freq - to 100MHz. Since the opamp's f_un is around 78MHz I have further reduced input sine frequency down to 1 meg while leaving the clock's frequency unchanged.
I would have pretended saying that capture, release times, together with non-zero on-resistance of the switch would resulted in some longer transients in the sampled signal. But here I am seeing that the opamp's output, ie the sampled version of the input sine, does not form a "ladder" as one can see in the first figure I have posted in the thread, but rather forms "pulse"-like waveform. That is why I am guessing that the problem is somewhere in the timing I have set.

 

[D.A.(Tony)Stewart]

You don’t have enough BW to switch this fast or excess Ciss, Coss. Check the tau= RdsOn*C is much less than expected latency + settling time

 

[danadakk]

At the most basic level a S/H looks something like this :

In your case you have no DC bias path for the OpAmp inv input, so that
results in very sensitive node to pickup, and with no bias unpredictable
OpAmp input diff amp operation.

If your C at input is leaky enough then you do have bias, but C leakage
very T sensitive.

https://www.analog.com/media/cn/training-seminars/tutorials/MT-090.pdf

 

[theguardian2001]

You don’t have enough BW to switch this fast or excess Ciss, Coss. Check the tau= RdsOn*C is much less than expected latency + settling time

Thank you, D.A.(Tony)Stewart, for your reply. Yes, reducing the clock frequency makes plots to look clearer. However, I am still not entirely sure why does sampled signal (the blue line on the plots) swings down instead of holding the sampled value until the next sample. Do you have any suggestions why this happens?
The second figure I am attaching is the same setup with the same opamp but using only ideal switches. So probably the inaccuracy can also be caused by switches I am using.

--- Updated Feb 20, 2025 ---

At the most basic level a S/H looks something like this :

View attachment 197505

In your case you have no DC bias path for the OpAmp inv input, so that
results in very sensitive node to pickup, and with no bias unpredictable
OpAmp input diff amp operation.

If your C at input is leaky enough then you do have bias, but C leakage
very T sensitive.

https://www.analog.com/media/cn/training-seminars/tutorials/MT-090.pdf

Thank you, danadakk, for your reply. I have seen the circuit you have attached. I like the one I am using because it "promises" to partially cancel the offset of the amplifier. But I will also try this one to see how it looks.

 

[D.A.(Tony)Stewart]

What's holding it back? Parasitic Capacitance Ciss,Coss. Your switches do not have enough BW.

 

[D.A.(Tony)Stewart]

To make this work t1 = t2 and t3 must be the inverse except open before close after t1 with switching off/on latency added to duty cycle but it is problematic with NFB.

I'd like to see the theoretical source of this.

--- Updated Feb 20, 2025 ---

Here is a simplified version using ideal Op Amp Ro=0 ohm, Iin=0 bias current to show the problems with negative feedback (NFB) https://tinyurl.com/2xjesrx4

SPDT is 0.1 ohm so added Rs so you can vary to see the interactive effects with your thumbwheel to adjust R or C. Very low input C added to simulate FET inputs

 

[theguardian2001]

To make this work t1 = t2 and t3 must be the inverse except open before close after t1 with switching off/on latency added to duty cycle but it is problematic with NFB.

I'd like to see the theoretical source of this.

--- Updated Feb 20, 2025 ---

Here is a simplified version using ideal Op Amp Ro=0 ohm, Iin=0 bias current to show the problems with negative feedback (NFB) https://tinyurl.com/2xjesrx4

SPDT is 0.1 ohm so added Rs so you can vary to see the interactive effects with your thumbwheel to adjust R or C. Very low input C added to simulate FET inputs

Regarding the source of the circuit - as I have mentioned earlier, it was taken from J.Baker "Mixed Signal Circuit design"

 

[theguardian2001]

Hello to everyone watching this thread!
I am still facing some difficulties in understanding how does opamp's BW is related to signal's and,what is more important, to switching frequency. The time since the last post in the thread I have spent on trying to implement a fully-differential topology of the S/H previously discussed. I have designed a fully differential opamp with CMFB with BW of around 70MHz and 55 degr. PM which I hoped would be enough to sample input signals up to 7MHz ish. The fully-differential S/H I am trying to test looks as follows with the same timing for all of the 3 switches discussed above:



To actually verify that I use the following setup which includes configuration of the circuit during all the 3 phases and to see how diff. output follows diff. input:



The graph shows that diff.output follows diff input with a really tiny phase shift and no distortions up to 20MHz and with tolerable distortions (meaning pretty small) up to 25MHz. But when I build up the circuit with ideal switches and this very opamp I see only small spikes in the differential output:

I have tried 1Mhz input and 10MHz sampling, 100kHz input with 1MHz sampling and the figure always looks like that. Obviously, ideal opamp implemented with 2 vcvs and ideal switches works perfect while keeping sampling and load caps sizes the same. I clearly see that something prevents v(sampled) taken from the load capacitors to reach the level of the input waveform. If I had used real switches, I would have said that what I see is charge injection only. Clearly output I am observing changes only during phi3 phase, but something causes to basically stay low during this phase as well.
Basically, my question is : Where does the charge diapers? When I am observing the bottom plates of the sampling capacitors I see how the nodes goes to zero during phi3. So maybe that is why the sampled signal is low - during phi3 bottom plates are zero and that is what is transferred to the output.

After trying to manipulate with the timing a bit a got the behavior I am expecting. However, when I try to keep the waveforms the same with a slight modification of the time they overlap the sampled waveform distorts. I can consider the thread (issue) to be solved.


The slightly modified clocks with its' corresponding sampled waveform.