Constraints on output ports and something about AMBA

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yangbay81983

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Hi,

when we make a sub-ip specification for DRAM controller before our RTL design, how to evaluate and add constraints on output ports who will be connected to SDRAM, Thanks! for example, set_load=?

Another question is the result of synthesis of AHB bus. Does it contain only Arbiter and Decoder? Once again, Thanks!

Yang
 

lakshman.ar said:
Normally 30% of the clock is specifed as the output delay.
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This 30% is special for ports for I/O? and other output delay should be calculated, is that right? Thanks
 

Could Anybody answer my question: how to add input/output delay constraints on input/output ports of IP who connect external environments ? Thanks
 

I thinks you should refer the SPEC to see the dealy requirement and consult with IP owner!
 
FOA if u have bought the IP frm some1 els, u cannot specify a input/output delay on those ports !

U have to consult the person who designed tht IP !

ur question : "Could Anybody answer my question: how to add input/output delay constraints on input/output ports of IP who connect external environments ?"

Please elaborate as to what it ur requirement, do u want to add a i/o delay constraints to the ports of IP ?
 

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